Table 5-6.
Memory Configuration Address Ranges and
Interleaving Sequences Encoded RAS Only
Physical Configuration
Address Ranges
Map Mode
Banks
Page Interleave Size
0F = 4x256KB, 6x1MB
000000-0FFFFFH
256KW/2WI
0, 1
400H
0F = 4x256KB, 6x1MB
100000-4FFFFFH
1MW/2WI
2, 3
800H
0F = 4x256KB, 6x1MB
500000-6FFFFFH
1MW/P
4
----
10 = 4x256KB, 8x1MB
000000-0FFFFFH
256KW/2WI
0, 1
400H
10 = 4x256KB, 8x1MB
100000-4FFFFFH
1MW/2WI
2, 3
800H
10 = 4x256KB, 8x1MB
500000-8FFFFFH
1MW/2WI
4, 5
800H
11 = 4x256KB, 10x1MB
000000-0FFFFFH
256KW/2WI
0, 1
400H
11 = 4x256KB, 10x1MB
100000-4FFFFFH
1MW/2WI
2, 3
800H
11 = 4x256KB, 10x1MB
500000-8FFFFFH
1MW/2WI
4, 5
800H
11 = 4x256KB, 10x1MB
900000-AFFFFFH
1MW/P
6
----
12 = 4x256KB, 12x1MB
000000-0FFFFFH
256KW/2WI
0, 1
400H
12 = 4x256KB, 12x1MB
100000-4FFFFFH
1MW/2WI
2, 3
800H
12 = 4x256KB, 12x1MB
500000-CFFFFFH
1MW/4WI
4-7
800H
13 = 10x1MB
000000-7FFFFFH
1MW/4WI
0-3
800H
13 = 10x1MB
800000-9FFFFFH
1MW/P
4
----
14 = 12x1MB
000000-7FFFFFH
1MW/4WI
0-3
800H
14 = 12x1MB
800000-BFFFFFH
1MW/2WI
4, 5
800H
15 = 14x1MB
000000-7FFFFFH
1MW/4WI
0-3
800H
15 = 14x1MB
800000-BFFFFFH
1MW/2WI
4, 5
800H
15 = 14x1MB
C00000-DFFFFFH
1MW/P
6
----
16 = 16x1MB
000000-7FFFFFH
1MW/4WI
0-3
800H
16 = 16x1MB
800000-FFFFFFH*
1MW/4WI
4-7
800H
* Top 128KB or 256KB accessible only via EMS.
Table 5-7.
Memory Configuration Address Ranges and
Interleaving Sequences Nonencoded RAS Only
Physical Configuration
Address Ranges
Map Mode
Banks
Page Interleave Size
17 = 4x256KB, 2x4MB
000000-0FFFFFH
256KW/2WI
0, 1
400H
17 = 4x256KB, 2x4MB
100000-8FFFFFH
4MW/P
2
----
18 = 2x1MB, 2x4MB
000000-7FFFFFH
4MW/P
1
----
18 = 2x1MB, 2x4MB
800000-9FFFFFH
1MW/P
0
----
19 = 4x4MB
000000-FFFFFFH*
4MW/2WI
0, 1
1000H
* Top 128KB or 256KB accessible only via EMS.
System Interface
DRAM Interface
I
Chips and Technologies, Inc.
P R E L I M I N A R Y
Revision 3.0
5-11