Single RAS Active (SRA), also known as shared CAS
In this mode, SCATsx provides four RAS signals and only two CAS signals for
controlling up to four DRAM banks. Each CAS drives four half-banks, so the CAS
signals should be buffered in systems having more than two banks. The buffering
adds delay which diminishes worst-case timing margins, particularly in 25MHz
systems. In addition, the sharing of CAS signals between banks means that only one
RAS signal can be allowed to remain active at one time. This adds an extra T-state
when switching between banks (as compared to MRA mode, which can switch banks
in zero wait states if the new bank already has its RAS signal active). The added
T-state represents a significant performance penalty. The only advantage of SRA
mode is that the external 74F153 and 74ALS138 aren’t needed, since the six CAS
signals become DREQs and DACKs, see Figure 5-1. Note: Signal names in
parentheses ( ) refer to SRA mode. Signal names without parentheses refer to MRA
mode.
74F244
-RAS3/MA10
MA10
-RAS3
74F153
74F153
+5V or GRND
91
92
93
94
95
96
100
101
134
89
43
45
47
48
90
46
44
XRST
(-DACK5)
(-DACK6)
(DRQ7)
(-RAS3)
(XRST)
*
20K
20K
20K
+5V
+5V
+5V
+5V
*
*
4.7K
DACKB (-DACK2)
DACKA (-DACK1)
DRQA
(DRQ2)
DRQB
(DRQ3)
DRQ3
DRQ7
DRQ5
YB
YA
EB
EA
I0A
S0
S1
DACK
L L
DACKA :
L
-DACK0
H
L H
H L
H H
-DACK1
-DACK2
-DACK5
-DACK7
-DACK3
-DACK6
( none )
DSEL
B A
L L
L H
H L
H H
DRQA
DRQB
DRQ0
DRQ1
DRQ2
DRQ3
DRQ5
DRQ6
DRQ7
GRND
74ALS138
74ALS138
82C836B
SCATsx
-CAS3L
-CAS1L
14
2
6
5
4
3
1
10
11
12
13
15
7
9
DSELB
(DRQ0)
DSELA
(DRQ1)
A0
A1
A2
E1
E2
E3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
(nc)
-DACK5
-DACK1
1
2
3
6
5
4
15
14
13
12
11
10
9
7
*
.
Figure 5-1.
MRA Mode Implementation
System Interface
DRAM Interface
I
Chips and Technologies, Inc.
P R E L I M I N A R Y
Revision 3.0
5-3