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參數(shù)資料
| 型號： | A42MX16-3BG100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 19/120頁 |
| 文件大小： | 854K |
| 代理商： | A42MX16-3BG100 |
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115
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.14.1.3
SPI Control Register – SPCR
Bit 7 - SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the
Global Interrupt Enable bit in SREG is set.
Bit 6 - SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
Bit 5 - DORD: Data ORDer
When the DORD bit is written to one, the LSB of the data word is transmitted first. When the
DORD bit is written to zero, the MSB of the data word is transmitted first.
Bit 4 - MSTR: MasTer/Slave Select Register
This bit selects Master SPI mode when written to logic one, and Slave SPI mode when written
logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable
SPI Master mode.
Bit 3 - CPOL: Clock POLarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to Figure 3-54 and Figure 3-55 on page 118 for an example. The CPOL func-
tionality is summarized in is summarized in Table 3-47.
Bit 2 - CPHA: Clock Phase
The setting of the Clock Phase bit (CPHA) determines if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to Figure 3-54 and Figure 3-55 on page 118 for an example.
The CPHA functionality is summarized below.
Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
osc is
shown in Table 3-49 on page 116.
Bit
765432
10
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
SPCR
Read/Write
R/WR/W
Initial Value
000000
00
Table 3-47.
CPOL Functionality
CPOL
Leading Edge
Trailing Edge
0
Rising
Falling
1
Falling
Rising
Table 3-48.
CPHA Functionality
CPHA
Leading Edge
Trailing Edge
0
Sample
Setup
1
Setup
Sample
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3PL100 | 40MX and 42MX FPGA Families |
| A42MX16-3PL100A | 40MX and 42MX FPGA Families |
| A42MX16-3PQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100 | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100A | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3BG100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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