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參數(shù)資料
| 型號(hào)： | A42MX16-3BG100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 35/120頁(yè) |
| 文件大小： | 854K |
| 代理商： | A42MX16-3BG100 |
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21
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Figure 3-9.
On-chip Data SRAM Access Cycles
3.6.3
I/O Memory
The I/O space definition of the ATA6289 is shown in Section 3.21.6 “Register Summary” on
page 181. All ATA6289 I/Os and peripherals are placed in the I/O space. All I/O locations may
be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the
32 general purpose working registers and the I/O space. I/O Registers within the address range
0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to Section
3.22 “Instruction Set Summary” on page 184 for more details. When using the I/O specific com-
mands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.
The ATA6289 is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O
space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be
used. For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other Atmel AVRs, the CBI and SBI instructions will only operate on the specified bit, and can
therefore be used on registers containing such Status Flags. The CBI and SBI instructions work
with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
3.6.4
General Purpose I/O Registers
The Atmel ATA6289 contains three General Purpose I/O Registers. These registers can be
used for storing any information, and they are particularly useful for storing global variables and
Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly
bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
clkCPU
T1
Data
RD
WR
Address valid
Compute Address
Next Instruction
Write
Read
Memory Access Instruction
Address
T2
T3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3PL100 | 40MX and 42MX FPGA Families |
| A42MX16-3PL100A | 40MX and 42MX FPGA Families |
| A42MX16-3PQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100 | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100A | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3BG100A | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100B | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100ES | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100M | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:40MX and 42MX FPGA Families |
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