參數(shù)資料
型號： A42MX16-3BG100
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 22/120頁
文件大小： 854K
代理商： A42MX16-3BG100
118
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Figure 3-55. SPI Transfer Format with CPHA = 1
3.15
Sensor Interface Block
The sensor interface block contains a Motion Sensor Interface Unit (MSIU), a Capacitance Sen-
sor Interface Unit (CSIU), a Voltage Sensor Interface Unit (VSIU), four control registers (SCR,
SCCR, SVCR, TSCR), an 8-bit programmable voltage reference calibration register (MSVCAL),
a Sensor Interrupt Mask Register (SIMSK), a Sensor Status and Flag Register (SSFR) and addi-
tionally an output multiplexer to select one of the two different signals f
C (output signal of CSIU)
and f
V (output signal of VSIU) for the output signal SENO. The output signal (SENO) is selected
by the SEN[1..0] bits in SCR Register. SENO is directed as input for Timer2, see Figure 3-29 on
page 81. The Capacitor / Voltage Sensor Interface Units in combination with the internal timer
modules Timer2 and Timer3 build an ADC to digitizing the different sensor signals, for example
from an external capacitance pressure sensor or an external capacitance acceleration/motion
sensor. Additionally, internal voltage levels can be measured and also an internal on-chip tem-
perature sensor can be monitored with the ADC. The general functionality of this ADC is
Channel (Pin) S2 can be either configured as motion wake-up with low power consumption or as
a normal capacitive sensor interface. For a motion wake-up application on pin S2 the capacitor
sensor interface must be disabled. If the capacitor sensor interface is enabled the internal cir-
cuitry forces periodically all sensor pins to GND. In that times all sensor pins are forced to GND,
no motion wake-up detection will occur, i.e. motion wake-up will fail.
If a motion/acceleration is detected the output signal of MSU (MSENOS) gets high and the
MSENO bit in the SSFR register is set (one), otherwise MSENOS is low and MSENO bit is
cleared (zero).
Additionally a motion sensor interrupt signal (SENINT) can be enabled if the MSIE bit in the
SIMSK register is set (one). The corresponding Interrupt Vector is executed if MSENF bit in
SSFR register is set (one). A more detailed description is given in the Section 3.15.1 “Motion
To ensure accurate results of sensor interface applications specific sleep mode configurations of
the Atmel ATA6289 needs to be done. Best results can be achieved for a motion wake-up appli-
cation if ATA6289 is configured into power-down mode. The performance of the capacitive
sensor interface is optimized if the ATA6289 is configured into sensor-noise reduction mode.
LSB
MSB
Bit 1
Bit 6
Bit 2
Bit 5
Bit 3
Bit 4
Bit 3
Bit 5
Bit 2
Bit 6
Bit 1
MSB
LSB
MSB first (DORD = 0)
LSB first (DORD =1)
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SS
SAMPLE -
MOSI/MISO
MISO - PIN
MOSI - PIN
相關(guān)PDF資料
PDF描述
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A42MX16-3PL100A 40MX and 42MX FPGA Families
A42MX16-3PQ100A 40MX and 42MX FPGA Families
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A42MX16-3VQ100A 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-3BG100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-3BG100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-3BG100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-3BG100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-3BG100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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