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參數(shù)資料
| 型號： | A42MX16-3BG100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 7/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-3BG100 |
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104
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
OVF
Timer/counter overflow
CP
Capture event signal
CPR
Capture event reset signal
T3CPE
Timer/counter capture signal
3.13.7.3
Timer3 Control Register A – T3CRA
Bit 7 - T3E: Timer3 Enable Bit
This bit controls the Timer3 block. The T3E bit must be written to logic one to enable Timer3,
and if the T3E bit is written to logic zero, the Timer3 is disabled.
Bit 6 - T3TS: Timer3 Toggle with Start Bit
The T3TS bit must be written to logic one to toggle the modulator output of Timer3 when the
timer is enabled with T3E. If the T3TS bit is written to logic zero, the modulator output of Timer3
is not toggled with the timer enable.
Bits 5..3 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 2 - T3CR: Timer3 Counter Reset
The T3CR Bit resets the Counter3 asynchronously if this bit is set to logic 1.
Bit 1 - T3SCE: Timer3 Software Capture Enable Bit
The T32SCE bit must be written to logic one to generate a software capture event. The T3SCE
bit is cleared after the counter value is saved in the capture register. The Timer3 counter value is
readable via its capture register during run time.
Bit 0 - T3AC: Timer3 Alternate Compare Register Sequence Bit
The T3AC bit must be written to logic one to enable the compare registers alternate mode, and if
the T3AC bit is written to logic zero, the alternate mode is disabled.
3.13.7.4
Timer3 Control Register B – T3CRB
Bit 7 - Res: Reserved Bit
This bit is reserved bit at the ATA6289 and will always read as zero.
Bit 6 - T3CPRM: Timer3 CaPture Reset Mask Bit
The T3CPRM bit must be written to logic one to enable the counter reset if an internal/external
capture event occurs, and if the T3CPRM bit is written to logic zero, the counter reset is
disabled.
Bit
76
54
32
10
T3E
T3TS
-
T3CR
T3SCE
T3AC
T3CRA
Read/Write
R/W
R
R/W
Initial Value
00
Bit
76
5
4
3
2
1
0
-
T3CPRM T3CRMB T3SAMB T3CTMB T3CRMA T3SAMA T3CTMA T3CRB
Read/Write
R
R/W
Initial Value
00
0
相關PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3PL100 | 40MX and 42MX FPGA Families |
| A42MX16-3PL100A | 40MX and 42MX FPGA Families |
| A42MX16-3PQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100 | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100A | 40MX and 42MX FPGA Families |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3BG100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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