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參數(shù)資料
| 型號： | A42MX16-3BG100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 54/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-3BG100 |
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39
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.8.1
Sleep Mode Control Register - SMCR
The Sleep Mode Control Register contains control bits for power management.
Bits 7..4 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bits 3, 2, 1 - SM2..0: Sleep Mode select Bits 2, 1, and 0
These bits select between the three available sleep modes as shown in Table 3-11.
Bit 0 - SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
3.8.2
Idle Mode
When all SM2 ...0 bits are written to zero, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing the SPI, LF-Receiver, Brown-out, Voltage Monitor, Sensor
Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep
mode basically halts CLK
CPU and CLKFLASH, while allowing the other clocks to run. Idle mode
enables the MCU to wake up from external triggered interrupts as well as internal ones like the
Timer Overflow and a transmit buffer empty interrupt or a receive buffer full interrupt of the
on-chip digital data modulator.
Bit
76
543210
-
SM2
SM1
SM0
SE
SMCR
Read/Write
RRRR
R/W
Initial Value
00
000000
Table 3-11.
Sleep Mode Select
SM2
SM1
SM0
Sleep Mode
00
0
Idle
0
1
Sensor Noise Reduction
0
1
0
Power-down (lowest current)
0
1
Reserved
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3PL100 | 40MX and 42MX FPGA Families |
| A42MX16-3PL100A | 40MX and 42MX FPGA Families |
| A42MX16-3PQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100 | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100A | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3BG100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3BG100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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