參數(shù)資料
型號(hào)： A42MX16-3BG100
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 50/120頁
文件大?。?/td> 854K
代理商： A42MX16-3BG100
35
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.7.5
Calibrated Internal Slow RC-Oscillator (SRC)
The calibrated internal SRC-Oscillator is a ultra low power oscillator providing a clock of 90 kHz.
During reset, hardware loads the calibration byte into the SRCCAL Register and thereby auto-
matically calibrates the SRC-Oscillator. Over a supply range of 1.9V to 3.6V and a temperature
range of –40°C to +85°C, the calibration gives a frequency of 90kHz ±10% (ensured by final
test). The oscillator can be calibrated to any frequency in the range of 81kHz – 99kHz within
±1% accuracy (typical value, not measured in final test) for a fixed supply voltage and tempera-
ture, by changing the SRCCAL register. This Oscillator can be used as Watchdog Oscillator,
Interval Timer, start measurement timer for Motion sensor, Reset Time-out and additionally also
as System clock.
3.7.5.1
Slow Frequency RC – Oscillator Calibration Register – SRCCAL
Bits 7..0 - SCAL7..0: Slow frequency RC-oscillator CALibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal FRC Oscillator to
remove process variations from the Oscillator frequency. The factory-calibrated value is auto-
matically written to this register during chip reset, giving an oscillator frequency of 90kHz. The
application software can write this register to change the oscillator frequency. The oscillator can
be calibrated to any frequency in the range of 81kHz to 99kHz within 1% accuracy for a fixed
supply voltage and temperature. Calibration outside that range is not guaranteed.
The SCAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-
quency ranges are overlapping, in other words a setting of SRCCAL = 0x7F gives a higher
frequency than SRCCAL = 0x80.
3.7.6
Clock Output Buffer
The device can output the system clock on the PC1/CLKO pin. To enable the output, the
CKOUT Fuse bit has to be programmed. This mode is suitable when the chip clock is used to
drive other circuits on the system. The clock also will be output during reset, and the normal
operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including
the internal RC Oscillators, can be selected when the clock is output on CLKO. If the System
Clock Prescaler is used, it is the divided system clock that is output.
Bit
7
6543
210
SCAL7 SCAL6
SCAL5
SCAL4
SCAL3
SCAL2
SCAL1
SCAL0
SRCCAL
Read/Write
R/W
Initial Value
0
0000
000
Table 3-8.
Device Clock Output Select Description
(1)
Device Clock Output
CKOUT Fuse
Clock Name
Description
PC1(CLKO)
1
CLK
disabled
0
CLK
enabled
Note:
1. For all fues
“1” means unprogrammed while “0” means programmed
相關(guān)PDF資料
PDF描述
A42MX16-3PL100 40MX and 42MX FPGA Families
A42MX16-3PL100A 40MX and 42MX FPGA Families
A42MX16-3PQ100A 40MX and 42MX FPGA Families
A42MX16-3VQ100 40MX and 42MX FPGA Families
A42MX16-3VQ100A 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-3BG100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-3BG100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-3BG100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-3BG100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-3BG100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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