- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16537 > AD9558/PCBZ (Analog Devices Inc)BOARD EVAL FOR AD9558 PDF資料下載
參數(shù)資料
| 型號： | AD9558/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9558 |
| 產(chǎn)品變化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 設(shè)計資源： | AD9558 Eval Brd BOM AD9558 Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁
Data Sheet
AD9558
Rev. B | Page 3 of 104
REVISION HISTORY
6/13—Rev. A to Rev. B
Changes to Multifunction Pins (M7 to M0) Section.................. 42
Change to Address 0x0101, Table 35 ............................................ 62
Changes to Bit 4, Table 43 .............................................................. 73
Updated Outline Dimensions......................................................104
4/12—Rev 0 to Rev. A
Changed 3 Hz to 352 kHz in Output Frequencies List Item,
Features Section................................................................................. 1
Change to Output Frequency Range Parameter, Min; and System
Clock Input Doubler Duty Cycle Parameter Description, Table 6... 6
Changes to Test Conditions/Comments Column, Table 9 .......... 8
Changes to Output Frequency Parameters, Min, Table 10 .......... 9
Changes to Pin 4 and Pin 42, Table 20 ......................................... 17
Changes to Device Register Programming When Using a Register
Setup File and Register Programming Overview Sections............. 26
Changed APLL VCO Lower Frequency and OUT5 Frequency
Range, Figure 35; Changed 225 MHz to 200 MHz and 3.45 GHz
to 3.35 GHz in Overview Section................................................... 29
Changes to Reference Profiles Section ......................................... 30
Changes to Programmable Digital Loop Filter Section ............. 32
Changes to System Clock Inputs Section..................................... 35
Changes to Output PLL (APLL) Section; Changes to Figure 39 .... 37
Changes to Figure 40; Changed 1024 to 1023 in Clock Dividers
Section; Changes to Clock Distribution Synchronization
Section .............................................................................................. 38
Changes to Multifunction Pins (M7 to M0) and IRQ Pin
Sections............................................................................................. 42
Changes to Figure 44 ...................................................................... 43
Changes to EEPROM Conditional Processing Section and
Figure 45............................................................................................ 46
Added Programming the EEPROM to Configure an M Pin
to Control Synchronization of Clock Distribution Section ......... 48
Changes to the Power Supply Partitions Section ........................ 58
Changed 89.5° to 88.5° in DPLL Phase Margin Section ............ 59
Changes to Address 0x0006, Address 0x0007, and
Address 0x000A, Table 35 .............................................................. 62
Changes to Address 0x0304, Table 35 .......................................... 63
Changes to Address 0x0405, Table 35 .......................................... 64
Changes to Address 0x071A and Address 0x071D, Table 35 .... 65
Changes to Address 0x0780, Address 0x0785 to
Address 0x078A, Address 0x079A, Address 0x079D, Table 35 ... 67
Changes to Address 0x07C0, Address 0x07DA, and
Address 0x07DD, Table 35............................................................. 68
Change to Address 0x0A01, Bit 7, Table 35................................. 69
Added Address 0x0E3D to Address 0x0E45, Table 35............... 71
Change to Table 38; Added Table 40, Renumbered Sequentially;
Changes to Table 41 ........................................................................ 72
Change to Bit 0, Address 0x0101, Table 43.................................. 73
Changes to Address 0x0304, Table 55 .......................................... 76
Deleted Address 0x0305, Table 55 ................................................ 76
Changes to Table Title, Table 63; Changes to Address 0x0400
and Address 0x0403, Table 64........................................................ 79
Changes to Address 0x0405, Table 64 .......................................... 80
Changes to Descriptions, Address 0x0500, Table 67.................. 81
Changes to Bit 0, Address 0x0501, Table 68 ................................ 82
Changes to Bits[6:4], Address 0x0505 and Changes to
Address 0x0506, Table 70............................................................... 83
Changes to Bits[6:4] and Bit 0, Address 0x050F, Table 73 ......... 84
Change to Address 0x0704, Table 78; Changes to Bits[3:0] in
Address 0x0707 and Address 070A, Table 79; and Changes to
Address 0x070E, Table 82................................................................ 87
Changes to Address 0x0710, Table 83; and Changes to Bits[3:0],
Address 0x0714, Table 84 ................................................................. 88
Changes to Bits[1:0], Address 0x0A01, Table 90........................... 89
Changes to Descriptions, Address 0x0A0B, Table 99................. 91
Changes to Bit 4, Address 0x0C06, Table 100 ............................. 93
Changes to Bit 6 and Bit 1, Address 0x0D01, Table 102 ............ 94
Changes to Table Summary, Table 114......................................... 98
Added Table 128............................................................................ 101
Changes to Table 129 .................................................................... 102
Changes to Table 130 .................................................................... 103
10/11—Revision 0: Initial Version
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GBM22DSAH | CONN EDGECARD 44POS R/A .156 SLD |
| DK-2632-03 | CABLE FIBER OPTIC DUAL LC-SC 3M |
| GEM30DTAS | CONN EDGECARD 60POS R/A .156 SLD |
| GMM12DRXI | CONN EDGECARD 24POS DIP .156 SLD |
| P1330R-105K | INDUCTOR POWER 1000.0UH SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9559 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| AD9559BCPZ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。