參數(shù)資料
型號： AD9558/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 95/104頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9558
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
設(shè)計資源： AD9558 Eval Brd BOM
AD9558 Schematic
標準包裝： 1
系列： *
AD9558
Data Sheet
Rev. B | Page 90 of 104
Reset Functions (Register 0x0A03)
Table 92. Reset Functions1
Address
Bits
Bit Name
Description
0x0A03
(autoclear)
7
Reserved
Default: 0b.
6
Clear LF
Setting this bit clears the digital loop filter (intended as a debug tool).
5
Clear CCI
Setting this bit clears the CCI filter (intended as a debug tool).
4
Reserved
Default: 0b.
3
Clear auto sync
Setting this bit resets the automatic synchronization logic (see Register 0x0500).
2
Clear TW history
Setting this bit resets the tuning word history logic (part of holdover functionality).
1
Clear all IRQs
Setting this bit clears the entire IRQ monitor register (Register 0x0D02 to Register 0x0D07).
It is the equivalent of setting all the bits of the IRQ clearing register (Register 0x0A04 to
Register 0x0A0D).
0
Clear watchdog timer
Setting this bit resets the watchdog timer (see Register 0x0211 and Register 0x0212). If the
timer times out, it starts a new timing cycle. If the timer has not yet timed out, it restarts at
time zero without causing a timeout event. Continuously resetting the watchdog timer at
intervals less than its timeout period prevents the watchdog timer from generating a timeout
event.
1
Note that all bits in this register are autoclearing.
IRQ Clearing (Register 0x0A04 to Register 0x0A09)
The IRQ clearing registers are identical in format to the IRQ monitor registers (Register 0x0D02 to Register 0x0D09). When set to logic 1,
an IRQ clearing bit resets the corresponding IRQ monitor bit, thereby canceling the interrupt request for the indicated event. The IRQ
clearing register is an autoclearing register.
Table 93. IRQ Clearing for SYSCLK
Address
Bits
Bit Name
Description
0x0A04
[7:6]
Reserved
5
SYSCLK unlocked
Clears SYSCLK unlocked IRQ
4
SYSCLK locked
Clears SYSCLK locked IRQ
3
APLL unlocked
Clears Output PLL unlocked IRQ
2
APLL locked
Clears Output PLL locked IRQ
1
APLL Cal ended
Clears APLL calibration complete IRQ
0
APLL Cal started
Clears APLL calibration started IRQ
Table 94. IRQ Clearing for Distribution Sync, Watchdog Timer, and EEPROM
Address
Bits
Bit Name
Description
0x0A05
[7:5]
Reserved
4
Pin program end
Clears pin program end IRQ
3
Sync clock distribution
Clears distribution sync IRQ
2
Watchdog timer
Clears watchdog timer IRQ
1
EEPROM fault
Clears EEPROM fault IRQ
0
EEPROM complete
Clears EEPROM complete IRQ
Table 95. IRQ Clearing for the Digital PLL
Address
Bits
Bit Name
Description
0x0A06
7
Switching
Clears switching IRQ
6
Closed
Clears closed IRQ
5
Freerun
Clears free run IRQ
4
Holdover
Clears holdover IRQ
3
Frequency unlocked
Clears frequency unlocked IRQ
2
Frequency locked
Clears frequency locked IRQ
1
Phase unlocked
Clears phase unlocked IRQ
0
Phase locked
Clears phase locked IRQ
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9559 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
AD9559/PCBZ 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9559BCPZ 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559BCPZ-REEL7 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559PCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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