參數(shù)資料
型號： AD9558/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 41/104頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9558
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
設(shè)計資源： AD9558 Eval Brd BOM
AD9558 Schematic
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
AD9558
Rev. B | Page 41 of 104
M3b DIVIDER/OUT5 PROGRAMMING IN FRAME
SYNCHRONIZATION MODE
In frame synchronization mode, the clock distribution signal path
for OUT5 is changed, as follows: the OUT5 signal goes from the RF
divider to the M0 divider, and then to the M3 and M3b dividers.
This means that in frame synchronization mode, the total divide
ratio between the RF divider and OUT5 is M0 × M3 × M3b.
The other important change is that the sync signal for the M3b
divider is no longer the standard clock distribution sync. It is
controlled by a signal derived from the input frame pulse.
OUPUT CLOCK
(OUT0)
FRAME CLOCK INPUT
(REFC/REFD)
ENABLE Fsync
(REGISTER 0x0640[0] = 1b)
FRAME SYNC ARM
(REGISTER OR SYNC PIN)
FRAME CLOCK
(OUT5)
ACTIVE SYNC
NOTES
1. AFTER THE FRAME SYNC IS ARMED, THE FRAME CLOCK OUTPUT IS SYNCHRONIZED TO THE FRAME CLOCK INPUT.
THE SKEW BETWEEN THE FRAME CLOCK INPUT AND FRAME CLOCK OUTPUT IS 15ns (NOMINAL) PLUS A DELAY OF 0.5 TO 1.5 OUTPUT CLOCK CYCLES.
09758-
141
Figure 41. Frame Synchronization in Level Sensitive Mode
ACTIVE SYNC
NOTES
1. AFTER THE FRAME SYNC IS ARMED, THE FRAME CLOCK OUTPUT IS SYNCHRONIZED TO THE FRAME CLOCK INPUT.
THE SKEW BETWEEN THE FRAME CLOCK INPUT AND FRAME CLOCK OUTPUT IS 15ns (NOMINAL) PLUS 0.5 TO 1.5 OUTPUT CLOCK CYCLES.
OUPUT CLOCK
(OUT0)
FRAME CLOCK INPUT
(REFC/REFD)
ENABLE Fsync
(REGISTER 0x0640[0] = 1b)
FRAME SYNC ARM
(REGISTER OR SYNC PIN)
FRAME CLOCK
(OUT5)
09758-
142
Figure 42. Frame Synchronization in One Shot Mode
FRAME SYNC PULSE INPUT (ON REFC OR REFD)
Fsync_arm (FROM EITHER THE SYNC PIN OR THE Arm Soft Fsync BIT IN REGISTER 0x0641[0])
RF
DIVIDER 1
CLOCK
DISTRIBUTION
SYNC LOGIC
M3 DIVIDER
M0 DIVIDER
M3b DIVIDER
FRAME SYNC
PULSE GENERATOR
ENABLE Fsync
OUT0
OUT5
LOGIC 0
DELAY
OUTPUT
SYNC
PULSE
OUTPUT
SYNC
LEVEL
(RETIMED)
ENABLE Fsync
NOTES
1. THE ENABLE Fsync FUNCTION IN THE DIAGRAM IS CONTROLLED BY REGISTER 0x0640[0].
ENABLE
Fsync
FROM
APLL
09758-
143
Figure 43. Frame Synchronization Implementation
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AD9559BCPZ-REEL7 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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