參數(shù)資料
型號: AD9558/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 8/104頁
文件大小: 0K
描述: BOARD EVAL FOR AD9558
產(chǎn)品變化通告: AD9558 Minor Metal Mask Change 17/Apr/2012
設計資源: AD9558 Eval Brd BOM
AD9558 Schematic
標準包裝: 1
系列: *
Data Sheet
AD9558
Rev. B | Page 11 of 104
DIGITAL PLL
Table 12.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DIGITAL PLL
Phase-Frequency Detector (PFD)
Input Frequency Range
2
100
kHz
Loop Bandwidth
0.1
2000
Hz
Programmable design parameter
Phase Margin
30
89
Degrees
Programmable design parameter
Closed-Loop Peaking
<0.1
dB
Programmable design parameter ;
part can be programmed for <0.1 dB peaking in
accordance with Telcordia GR-253 jitter transfer
Reference Input (R) Division Factor
1
220
1, 2, …, 1,048,576
Integer Feedback (N1) Division Factor
180
217
180, 181, …, 131,072
Fractional Feedback Divide Ratio
0
0.999
Maximum value: 16,777,215/16,777,216
DIGITAL PLL LOCK DETECTION
Table 13.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PHASE LOCK DETECTOR
Threshold Programming Range
0.001
65.5
ns
Threshold Resolution
1
ps
FREQUENCY LOCK DETECTOR
Threshold Programming Range
0.001
16,700
ns
Reference-to-feedback period difference
Threshold Resolution
1
ps
HOLDOVER SPECIFICATIONS
Table 14.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
HOLDOVER SPECIFICATIONS
Initial Frequency Accuracy
<0.01
ppm
Excludes frequency drift of SYSCLK source;
excludes frequency drift of input reference prior
to entering holdover; compliant with GR-1244
Stratum 3
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
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AD9559BCPZ-REEL7 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559PCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator