參數(shù)資料
型號(hào)： AD9558/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 64/104頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR AD9558
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
設(shè)計(jì)資源： AD9558 Eval Brd BOM
AD9558 Schematic
標(biāo)準(zhǔn)包裝： 1
系列： *
AD9558
Data Sheet
Rev. B | Page 62 of 104
REGISTER MAP
Register addresses that are not listed in Table 35 are not used, and writing to those registers has no effect. The user should write the
default value to sections of registers marked reserved. R = read-only. A = autoclear. E = excluded from EEPROM loading. L = live (I/O
update not required for register to take effect or for a read-only register to be updated).
Table 35. Register Map
Reg
Addr
(Hex)
Opt
Name
D7
D6
D5
D4
D3
D2
D1
D0
Def
Serial Control Port Configuration and Part Identification
0x0000
L, E
SPI control
SDO enable
LSB first/
increment
address
Soft reset
Reserved
00
0x0000
L
IC control
Reserved
Soft reset
Reserved
00
0x0004
Readback
control
Reserved
Read buffer
register
00
0x0005
A, L
I/O update
Reserved
I/O update
00
0x0006
L
User scratch
pad
User scratch pad[7:0]
00
0x0007
L
User scratch pad[15:8]
00
0x000A
R, L
Silicon rev
Silicon revision[7:0]
21
0x000B
R, L
Reserved
0F
0x000C
R, L
Part ID
Clock part family ID[7:0]
01
0x000D
R, L
Clock part family ID[15:8]
00
System Clock
0x0100
SYSCLK config
PLL feedback
divider
System clock N divider[7:0]
08
0x0101
Reserved
Load from
ROM (read-
only)
SYSCLK XTAL
enable
SYSCLK P divider[1:0]
SYSCLK
doubler
enable
09
or
19
0x0102
Reserved
00
0x0103
SYSCLK period
Nominal system clock period (fs), Bits[7:0] (1 ns at 1 ppm accuracy)
0E
0x0104
Nominal system clock period (fs), Bits[15:8] (1 ns at 1 ppm accuracy)
67
0x0105
Reserved
Nominal system clock period (fs), Bits[20:16]
13
0x0106
SYSCLK
stability
System clock stability period (ms), Bits[7:0]
32
0x0107
System clock stability period (ms), Bits[15:8]
00
0x0108
A
Reserved
Reset
SYSCLK
stab timer
(autoclear)
System clock stability period (ms), Bits[19:16]
(not autoclearing)
00
General Configuration
0x0200
EN_MPIN
Reserved
Enable M pins
and IRQ pin
function
00
0x0201
M0FUNC
Output/
A
input
E
Function[6:0]
B0
0x0202
M1FUNC
Output/A
A
input
E
Function[6:0]
B1
0x0203
M2FUNC
Output/A
A
input
E
Function[6:0]
C0
0x0204
M3FUNC
Output/A
A
input
E
Function[6:0]
C1
0x0205
M4FUNC
Output/A
A
input
E
Function[6:0]
B2
0x0206
M5func
Output/A
A
input
E
Function[6:0]
B3
0x0207
M6FUNC
Output/A
A
input
E
Function[6:0]
C2
0x0208
M7FUNC
Output/A
A
input
E
Function[6:0]
C3
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AD9559 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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AD9559BCPZ 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559BCPZ-REEL7 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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