參數(shù)資料
型號： AD9558/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 84/104頁
文件大小： 0K
描述： BOARD EVAL FOR AD9558
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
設(shè)計資源： AD9558 Eval Brd BOM
AD9558 Schematic
標(biāo)準(zhǔn)包裝： 1
系列： *
AD9558
Data Sheet
Rev. B | Page 80 of 104
Address
Bits
Bit Name
Description
[2:0]
Pole 1 Cp1.
Cp1 (pF)
Bit 2
Bit 1
Bit 0
0
20
80
100
20
40
100
120 (default)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0x0404
[7:1]
Reserved
Default: 0x00.
0
Bypass internal Rzero
0 (default) = uses the internal Rzero resistor.
1 = bypasses the internal Rzero resistor (makes Rzero = 0 and requires the use of a series
external zero resistor).
0x0405
[7:4]
Reserved
Default: 0x2.
3
APLL locked controlled
sync
0 (default) = the clock distribution sync function is not enabled until the output PLL (APLL) is
calibrated and locked. After APLL calibration and lock, the output clock distribution sync is
armed, and the sync function for the clock outputs is under the control of Register 0x0500.
1 = overrides the lock detector state of the output PLL; allows Register 0x0500 to control
the output sync function, regardless of the APLL lock status.
[2:1]
Reserved
Default: 00b.
0
Manual APLL
VCO calibration
1 = initiates VCO calibration. (Calibration occurs on low-to-high transition.)
0 (default) = does nothing. This is not an autoclearing bit.
1
Note that the default APLL loop BW is 180 KHz.
Table 65. Reserved
Address
Bits
Bit Name
Description
0x0406
[7:0]
Reserved
Default: 0x00
Table 66. RF Divider Setting
Address
Bits
Bit Name
Description
0x0407
[7:4]
RF Divider 2 division
0000/0001 = 3
0010 = 4
0011 = 5
0100 = 6 (default)
0101 = 7
0110 = 8
0111 = 9
1000 = 10
1001 = 11
[3:0]
RF Divider 1 division
0000/0001 = 3
0010 = 4
0011 = 5
0100 = 6 (default)
0101 = 7
0110 = 8
0111 = 9
1000 = 10
1001 = 11
0x0408
[7:5]
Reserved
Reserved. Default: 000b
4
RF divider start-up mode
0 (default) = RF dividers are held in power-down until the APLL feedback divider is
detected, which ensures proper RF divider operation when exiting full power-down
1 = RF dividers are not held in power-down until the APLL feedback divider is detected
[3:2]
Reserved
Reserved. Default: 00b
1
PD RF Divider 2
0 = enables RF Divider 2
1 (default) = powers down RF Divider 2
0
PD RF Divider 1
0 (default) = enables RF Divider 1
1 = powers down RF Divider 1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9559 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
AD9559/PCBZ 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
AD9559BCPZ 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559BCPZ-REEL7 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
AD9559PCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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