參數(shù)資料
型號: AD9558/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 79/104頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9558
產(chǎn)品變化通告: AD9558 Minor Metal Mask Change 17/Apr/2012
設(shè)計資源: AD9558 Eval Brd BOM
AD9558 Schematic
標(biāo)準(zhǔn)包裝: 1
系列: *
AD9558
Data Sheet
Rev. B | Page 76 of 104
Table 52. IRQ Mask for Reference Inputs
Address
Bits
Bit Name
Description
0x020E
7
Reserved
6
REFB validated
Enables IRQ for indicating that REFB has been validated
5
REFB fault cleared
Enables IRQ for indicating that REFB has been cleared of a previous fault
4
REFB fault
Enables IRQ for indicating that REFB has been faulted
3
Reserved
2
REFA validated
Enables IRQ for indicating that REFA has been validated
1
REFA fault cleared
Enables IRQ for indicating that REFA has been cleared of a previous fault
0
REFA fault
Enables IRQ for indicating that REFA has been faulted
0x020F
[7:0]
Reserved
Table 53. Watchdog Timer 11
Address
Bits
Bit Name
Description
0x0210
[7:0]
Watchdog timer (ms)
Watchdog timer, Bits[7:0]; default: 0x00
0x0211
[7:0]
Watchdog timer, Bits[15:8]; default: 0x00
1
Note that the watchdog timer is expressed in units of milliseconds (ms). The default value is 0 (disabled).
DPLL CONFIGURATION (REGISTER 0x0300 TO REGISTER 0x032E)
Table 54. Free Run Frequency Tuning Word1
Address
Bits
Bit Name
Description
0x0300
[7:0]
30-bit free run frequency tuning word
Free run frequency tuning word, Bits[7:0]; default: 0x11
0x0301
[7:0]
Free run frequency tuning word, Bits[15:8]; default: 0x15
0x0302
[7:0]
Free run frequency tuning word, Bits[23:9]; default: 0x64
0x0303
[7:6]
Reserved
[5:0]
30-bit free run frequency word
Free run frequency tuning word, Bits[29:24]; default: 0x1B
1
Note that the default free run tuning word is 0x1B641511, which is used for 8 kHz/19.44 MHz = 622.08 MHz translation.
Table 55. Digital Oscillator Control
Address
Bits
Bit Name
Description
0x0304
[7:6]
Reserved
Default: 00b
5
DCO 4-level output
0 (default) = DCO 3-level output mode
1 = enables DCO 4-level output mode
4
Reserved
Reserved (must be set to 1b)
[3:0]
Reserved
Reserved (default: 0x0)
Table 56. DPLL Frequency Clamp
Address
Bits
Bit Name
Description
0x0306
[7:0]
Lower limit of pull-in range (expressed
as a 20-bit frequency tuning word)
Lower limit pull-in range, Bits[7:0].
Default: 0x51.
0x0307
[7:0]
Lower limit pull-in range, Bits[15:8].
Default: 0xB8.
0x0308
[7:4]
Reserved
Default: 0x0.
[3:0]
Lower limit of pull-in range
Lower limit pull-in range, Bits[19:16].
Default: 0x2.
0x0309
[7:0]
Upper limit of pull-in range
(expressed as a 20-bit frequency
tuning word)
Upper limit pull-in range, Bits[7:0].
Default: 0x3E.
0x030A
[7:0]
Upper limit pull-in range, Bits[15:8].
Default: 0x0A.
0x030B
[7:4]
Reserved
Default: 0x0.
[3:0]
Upper limit of pull-in range
Upper limit pull-in range, Bits[19:16].
Default: 0xB.
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