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參數(shù)資料
| 型號： | AD9558/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 98/104頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9558 |
| 產(chǎn)品變化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 設(shè)計(jì)資源： | AD9558 Eval Brd BOM AD9558 Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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Data Sheet
AD9558
Rev. B | Page 93 of 104
Address
Bits
Bit Name
Description
0x0C05
[7:4]
Reserved
Reserved.
[3:2]
Channel 1 output frequency
scale
Scales the selected output frequency (defined by Register 0x0C01[7:4]) for the Channel
Divider 1 output.
00 (default) = divide-by-1.
01 = divide-by-4.
10 = divide-by-8.
11 = divide-by-16.
[1:0]
Channel 0 output frequency
scale
Scale the selected output frequency (defined by Register 0x0C01[7:4]) for the Channel
Divider 0 output.
00 (default) = divide-by-1.
01 = divide-by-4.
10 = divide-by-8.
11 = divide-by-16.
0x0C06
[7:5]
Reserved
Reserved.
4
Sel high PM base loop filter
0 = base loop filter with normal (70°) phase margin (default).
1 = base loop filter with high (88.5°) phase margin.
(< 0.1 dB peaking in closed-loop transfer function).
[3:2]
DPLL loop BW
Scale the DPLL loop BW while in soft pin mode.
00 (default) = 50 Hz.
01 = 1 Hz.
10 = 10 Hz.
11 =100 Hz.
[1:0]
Reference input frequency
tolerance
Scales the input frequency tolerance while in soft pin mode.
00 (default) = outer tolerance: 10%; inner tolerance: 8% (for general conditions).
01 = outer tolerance: 12 ppm; inner tolerance: 9.6 ppm (for Stratum 3).
10 = outer tolerance: 48 ppm; inner tolerance: 38 ppm (for SMC clock standard).
11 = outer tolerance: 200 ppm; inner tolerance: 160 ppm (for XTAL system clock).
0x0C07
[7:1]
Reserved
Reserved.
0
Soft pin start transfer
Autoclearing register. 1 = initiates ROM download without resetting the part/register map.
After ROM download is complete, this register is reset.
0x0C08
[7:1]
Reserved
Reserved.
0
Soft pin reset
Autoclearing register; resets the part like soft reset (Register 0x0000[5]), except that this
reset function initiates a soft pin ROM download without resetting the part/register map.
After ROM download is complete, this register is pulled back to zero.
1
All bits in Register 0x0C00 to Register 0x0C06 take effect only with either a soft pin start transfer (Register 0x0C07) or soft pin reset (Register 0x0C08).
STATUS READBACK (REGISTER 0x0D00 TO REGISTER 0x0D14)
All bits in Register 0x0D00 to Register 0x0D14 are read only. To show the latest status, these registers require an I/O update (Register 0x0005 =
0x01) immediately before being read.
Table 101. EEPROM Status
Address
Bits
Bit Name
Description
0x0D00
[7:4]
Reserved
Reserved.
3
Pin program ROM load process
The control logic sets this bit when data is being read from the ROM.
2
Fault detected
An error occurred while saving data to or loading data from the EEPROM.
1
Load in progress
The control logic sets this bit while data is being read from the EEPROM.
0
Save in progress
The control logic sets this bit while data is being written to the EEPROM.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9559 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| AD9559BCPZ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
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