參數(shù)資料
型號(hào)： ADSP-21160MKBZ-80
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/52頁(yè)
文件大小： 0K
描述： IC DSP CONTROLLER 32BIT 400 BGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類(lèi)型： 浮點(diǎn)
接口： 主機(jī)接口，連接端口，串行端口
時(shí)鐘速率： 80MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 2.50V
工作溫度： 0°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 400-BBGA
供應(yīng)商設(shè)備封裝： 400-PBGA（27x27）
包裝： 托盤(pán)
ADSP-21160M
–10–
REV. 0
BRST
I/O/T
Sequential Burst Access. BRST is asserted by ADSP-21160M or a host to indicate that
data associated with consecutive addresses is being read or written. A slave device
samples the initial address and increments an internal address counter after each
transfer. The incremented address is not pipelined on the bus. If the burst access is a
read from host to ADSP-21160M, ADSP-21160M automatically increments the
address as long as BRST is asserted. BRST is asserted after the initial access of a burst
transfer. It is asserted for every cycle after that, except for the last data request cycle
(denoted by RDx or WRx asserted and BRST negated). A keeper latch on the DSP’s
BRST pin maintains the input at the level it was last driven (only enabled on the
ADSP-21160M with ID2–0 = 00x).
ACK
I/O/S
Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to
an external memory access. ACK is used by I/O devices, memory controllers, or other
peripherals to hold off completion of an external memory access. The ADSP-21160M
deasserts ACK as an output to add wait states to a synchronous access of its internal
memory. A keeper latch on the DSP’s ACK pin maintains the input at the level it was
last driven (only enabled on the ADSP-21160M with ID2–0 = 00x).
SBTS
I/S
Suspend Bus and Three-State. External devices can assert SBTS (low) to place the
external bus address, data, selects, and strobes in a high impedance state for the
following cycle. If the ADSP-21160M attempts to access external memory while SBTS
is asserted, the processor will halt and the memory access will not be completed until
SBTS is deasserted. SBTS should only be used to recover from host processor and/or
ADSP-21160M deadlock or used with a DRAM controller.
IRQ2–0
I/A
Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be
either edge-triggered or level-sensitive.
FLAG3–0
I/O/A
Flag Pins. Each is configured via control bits as either an input or output. As an input,
it can be tested as a condition. As an output, it can be used to signal external peripherals.
TIMEXP
O
Timer Expired. Asserted for four CLKIN cycles when the timer is enabled and
TCOUNT decrements to zero.
HBR
I/A
Host Bus Request. Must be asserted by a host processor to request control of the
ADSP-21160M’s external bus. When HBR is asserted in a multiprocessing system, the
ADSP-21160M that is bus master will relinquish the bus and assert HBG. To relinquish
the bus, the ADSP-21160M places the address, data, select, and strobe lines in a high
impedance state. HBR has priority over all ADSP-21160M bus requests (BR6–1) in a
multiprocessing system.
HBG
I/O
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor
may take control of the external bus. HBG is asserted (held low) by the ADSP-21160M
until HBR is released. In a multiprocessing system, HBG is output by the
ADSP-21160M bus master and is monitored by all others.
CS
I/A
Chip Select. Asserted by host processor to select the ADSP-21160M.
REDY
O (O/D)
Host Bus Acknowledge. The ADSP-21160M deasserts REDY (low) to add waitstates
to a host access when CS and HBR inputs are asserted.
DMAR1
I/A
DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA
services.
DMAR2
I/A
DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA
services.
ID2–0
I
Multiprocessing ID. Determines which multiprocessing bus request (BR1–BR6) is used
by ADSP-21160M. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and
so on. Use ID = 000 or ID = 001 in single-processor systems. These lines are a system
configuration selection which should be hardwired or only changed at reset.
DMAG1
O/T
DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21160M to indicate that the
requested DMA starts on the next cycle. Driven by bus master only.
Table 2. Pin Function Descriptions (Continued)
Pin
Type
Function
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