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參數(shù)資料
| 型號： | ADSP-21160MKBZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 400 BGA |
| 產(chǎn)品培訓模塊： | SHARC Processor Overview |
| 標準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | 主機接口，連接端口，串行端口 |
| 時鐘速率： | 80MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-BBGA |
| 供應商設備封裝： | 400-PBGA（27x27） |
| 包裝： | 托盤 |
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ADSP-21160M
Timing Specifications
The ADSP-21160M’s internal clock switches at higher fre-
quencies than the system input clock (CLKIN). To generate
the internal clock, the DSP uses an internal phase-locked
loop (PLL). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the DSP’s
internal clock (the clock source for the external port logic
and I/O pads).
The ADSP-21160M’s internal clock (a multiple of CLKIN)
provides the clock signal for timing internal memory,
processor core, link ports, serial ports, and external port (as
required for read/write strobes in asynchronous access
mode). During reset, program the ratio between the DSP’s
internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG3–0 pins. Even though the
internal clock is the clock source for the external port, the
external port clock always switches at the CLKIN fre-
quency. To determine switching frequencies for the serial
and link ports, divide down the internal clock, using the
programmable divider control of each port (TDIVx/RDIVx
for the serial ports and LxCLKD1–0 for the link ports).
Note the following definitions of various clock periods that
are a function of CLKIN and the appropriate ratio control:
t
CCLK = (tCK) / CR
t
LCLK = (tCCLK)
LR
t
SCLK = (tCCLK)
SR
Where:
LCLK = Link Port Clock
SCLK = Serial Port Clock
t
CK = CLKIN Clock Period
t
CCLK = (Processor) Core Clock Period
t
LCLK = Link Port Clock Period
t
SCLK = Serial Port Clock Period
CR = Core/CLKIN Ratio (2, 3, or 4:1,
determined by CLK_CFG3–0 at reset)
LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1,
determined by LxCLKD)
SR = Serial Port/Core Clock Ratio (wide range,
determined by
CLKDIV)
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of
others. While addition or subtraction would yield meaning-
ful results for an individual device, the values given in this
data sheet reflect statistical variations and worst cases. Con-
sequently, it is not meaningful to add parameters to derive
longer times.
See Figure 32 under Test Conditions for voltage reference
levels.
Switching Characteristics specify how the processor
changes its signals. Circuitry external to the processor must
be designed for compatibility with these signal characteris-
tics. Switching characteristics describe what the processor
will do in a given circumstance. Use switching characteris-
tics to ensure that any timing requirement of a device
connected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled
by circuitry external to the processor, such as the data input
for a read operation. Timing requirements guarantee that
the processor operates correctly with other devices.
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| ADSP-21160N | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21160NCB-100 | 功能描述:IC DSP CONTROLLER 32BIT 400BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21160NCB-TBD | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
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| ADSP-21160NCE-100 | 制造商:Analog Devices 功能描述: |
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