- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19373 > ADSP-21160MKBZ-80 (Analog Devices Inc)IC DSP CONTROLLER 32BIT 400 BGA PDF資料下載
參數(shù)資料
| 型號： | ADSP-21160MKBZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 49/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 400 BGA |
| 產(chǎn)品培訓(xùn)模塊： | SHARC Processor Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | 主機接口，連接端口，串行端口 |
| 時鐘速率： | 80MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-BBGA |
| 供應(yīng)商設(shè)備封裝： | 400-PBGA（27x27） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁當(dāng)前第49頁第50頁第51頁第52頁
ADSP-21160M
–6–
REV. 0
transmit and receive functions provide greater flexibility for
serial communications. Serial port data can be automati-
cally transferred to and from on-chip memory via a
dedicated DMA. Each of the serial ports offers a TDM
multichannel mode. The serial ports can operate with lit-
tle-endian or big-endian transmission formats, with word
lengths selectable from 3 bits to 32 bits. They offer selectable
synchronization and transmit modes as well as optional
-law or A-law companding. Serial port clocks and frame
syncs can be internally or externally generated.
Host Processor Interface
The ADSP-21160M host interface allows easy connection
to standard microprocessor buses, both 16-bit and 32-bit,
with little additional hardware required. The host interface
is accessed through the ADSP-21160M’s external port and
is memory-mapped into the unified address space. Four
channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead. The host processor communicates with the
ADSP-21160M’s external bus with host bus request
(HBR), host but grant (HBG), ready (REDY), acknowledge
(ACK), and chip select (CS) signals. The host can directly
read and write the internal memory of the ADSP-21160M,
and can access the DMA channel setup and mailbox regis-
ters. Vector interrupt support provides efficient execution
of host commands.
Program Booting
The internal memory of the ADSP-21160M can be booted
at system power-up from an 8-bit EPROM, a host proces-
sor, or through one of the link ports. Selection of the boot
source is controlled by the BMS (Boot Memory Select),
EBOOT (EPROM Boot), and LBOOT (Link/Host Boot)
pins. 32-bit and 16-bit host processors can be used
for booting.
Phased Locked Loop
The ADSP-21160M uses an on-chip PLL to generate the
internal clock for the core. Ratios of 2:1, 3:1, and 4:1
between the core and CLKIN are supported. The
CLK_CFG pins are used to select the ratio. The CLKIN
rate is the rate at which the synchronous external
port operates.
Power Supplies
The ADSP-21160Mhas separate power supply connections
for the internal (V
DDINT), external (VDDEXT), and analog
(AV
DD/AGND) power supplies. The internal and analog
supplies must meet the 2.5 V requirement. The external
supply must meet the 3.3 V requirement. All external supply
pins must be connected to the same supply.
Note that the analog supply (AV
DD) powers the
ADSP-21160M’s clock generator PLL. To produce a stable
clock, the system must provide an external circuit to filter
the power input to the AV
DD pin. Place the filter as close as
possible to the pin. For an example circuit, see Figure 5. To
prevent noise coupling, use a wide trace for the analog
ground (AGND) signal and install a decoupling capacitor
as close as possible to the pin.
Figure 4. Shared Memory Multiprocessing System
$''5±
'$7$ ±
3$
%06
&21752/
$'63[
3$
%5 %5±
%5
&21752/
$'63[
$''5±
'$7$ ±
3$
%5± %5±
%5
&21752/
$'63[
,'±
5(6(7
53%$
&/.,1
,'±
5(6(7
53%$
,'±
5(6(7
53%$
&/.,1
$'63[
&/2&.
5(6(7
$''5
'$7$
+2 67
352 &( 662 5
,1 7( 5 )$&(
23 7,21 $/
$&.
*/2%$/
0( 02 5<
$1 '
3( 5,3+ (5$/6
23 7,21 $/
2(
$''5
'$7 $
&6
$''5
'$7$
%22 7 (35 20
23 7,21 $/
5';
06±
6%76
&/.287
&6
$&.
$'' 5±
'$7$ ±
&/.,1
3$*(
%5
%5±
5('<
+%*
+%5
&6
:(
:5;
&
2
17
52
/
$'
'
5
(
6
'$
7
$
&
2
17
52
/
$
'
5
(66
'$
7
$
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AYM25DTBD | CONN EDGECARD 50POS R/A .156 SLD |
| ADSP-TS203SABPZ050 | IC PROCESSOR 500MHZ 576BGA |
| ASM25DTBD | CONN EDGECARD 50POS R/A .156 SLD |
| ADSP-21160NKBZ-100 | IC DSP CONTROLLER 32BIT 400-BGA |
| ADSP-21062LCSZ-160 | IC DSP CONTROLLER 32BIT 240MQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21160N | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21160NCB-100 | 功能描述:IC DSP CONTROLLER 32BIT 400BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21160NCB-TBD | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21160NCBZ-100 | 功能描述:IC DSP CONTROLLER 32BIT 400-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21160NCE-100 | 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。