參數(shù)資料
型號(hào)： ADSP-21160MKBZ-80
廠商： Analog Devices Inc
文件頁數(shù)： 3/52頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 32BIT 400 BGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，連接端口，串行端口
時(shí)鐘速率： 80MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 2.50V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 400-BBGA
供應(yīng)商設(shè)備封裝： 400-PBGA（27x27）
包裝： 托盤
–11–
REV. 0
ADSP-21160M
DMAG2
O/T
DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160M to indicate that the
requested DMA starts on the next cycle. Driven by bus master only.
BR6–1
I/O/S
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21160Ms to arbitrate
for bus mastership. An ADSP-21160M only drives its own BRx line (corresponding to
the value of its ID2–0 inputs) and monitors all others. In a multiprocessor system with
less than six ADSP-21160Ms, the unused BRx pins should be pulled high; the
processor’s own BRx line must not be pulled high or low because it is an output.
RPBA
I/S
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for
multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected.
This signal is a system configuration selection which must be set to the same value on
every ADSP-21160M. If the value of RPBA is changed during system operation, it must
be changed in the same CLKIN cycle on every ADSP-21160M.
PA
I/O/T
Priority Access. Asserting its PA pin allows an ADSP-21160M bus slave to interrupt
background DMA transfers and gain access to the external bus. PA is connected to all
ADSP-21160Ms in the system. If access priority is not required in a system, the PA pin
should be left unconnected.
DTx
O
Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 k
internal pull-up resistor.
DRx
I
Data Receive (Serial Ports 0, 1). Each DR pin has a 50 k
internal pull-up resistor.
TCLKx
I/O
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 k
internal
pull-up resistor.
RCLKx
I/O
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 k
internal pull-up resistor.
TFSx
I/O
Transmit Frame Sync (Serial Ports 0, 1).
RFSx
I/O
Receive Frame Sync (Serial Ports 0, 1).
LxDAT7–0
I/O
Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 k
internal pull-down
resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.
LxCLK
I/O
Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 k
internal pull-down
resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1register.
LxACK
I/O
Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 k
internal
pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register.
EBOOT
I
EPROM Boot Select. For a description of how this pin operates, see Table 3. This
signal is a system configuration selection that should be hardwired.
LBOOT
I
Link Boot. For a description of how this pin operates, see Table 3. This signal is a
system configuration selection that should be hardwired.
BMS
I/O/T
Boot Memory Select. Serves as an output or input as selected with the EBOOT and
LBOOT pins; see Table 3. This input is a system configuration selection that should
be hardwired.
CLKIN
I
Local Clock In. CLKIN is the ADSP-21160M clock input. The ADSP-21160M
external port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple
of the CLKIN frequency; it is programmable at power-up. CLKIN may not be halted,
changed, or operated below the specified frequency.
CLK_CFG3–0
I
Core/CLKIN Ratio Control. ADSP-21160M core clock (instruction cycle) rate is equal
to n
CLKIN where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0 inputs.
For clock configuration definitions, see the RESET & CLKIN section of the System
Design chapter of the ADSP-21160 SHARC DSP Hardware Reference manual.
CLKOUT
O/T
Local Clock Out. CLKOUT is driven at the CLKIN frequency by the current bus
master. This output is three-stated when the ADSP-21160M is not the bus master, or
when the host controls the bus (HBG asserted). A keeper latch on the DSP’s CLKOUT
pin maintains the output at the level it was last driven (only enabled on the
ADSP-21160M with ID2–0 = 00x).
RESET
I/A
Processor Reset. Resets the ADSP-21160M to a known state and begins execution at
the program memory location specified by the hardware reset vector address. The
RESET input must be asserted (low) at power-up.
Table 2. Pin Function Descriptions (Continued)
Pin
Type
Function
相關(guān)PDF資料
PDF描述
AYM25DTBD CONN EDGECARD 50POS R/A .156 SLD
ADSP-TS203SABPZ050 IC PROCESSOR 500MHZ 576BGA
ASM25DTBD CONN EDGECARD 50POS R/A .156 SLD
ADSP-21160NKBZ-100 IC DSP CONTROLLER 32BIT 400-BGA
ADSP-21062LCSZ-160 IC DSP CONTROLLER 32BIT 240MQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21160N 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
ADSP-21160NCB-100 功能描述:IC DSP CONTROLLER 32BIT 400BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21160NCB-TBD 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
ADSP-21160NCBZ-100 功能描述:IC DSP CONTROLLER 32BIT 400-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
ADSP-21160NCE-100 制造商:Analog Devices 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*