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參數(shù)資料
| 型號(hào)： | ADSP-21160MKBZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 45/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 400 BGA |
| 產(chǎn)品培訓(xùn)模塊： | SHARC Processor Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | 主機(jī)接口，連接端口，串行端口 |
| 時(shí)鐘速率： | 80MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-BBGA |
| 供應(yīng)商設(shè)備封裝： | 400-PBGA（27x27） |
| 包裝： | 托盤 |
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ADSP-21160M
host processor, other ADSP-21160Ms, memory or I/O
transfers). Programs can be downloaded to the
ADSP-21160M using DMA transfers. Asynchronous
off-chip peripherals can control two DMA channels using
DMA Request/Grant lines (DMAR1–2, DMAG1–2).
Other DMA features include interrupt generation upon
completion of DMA transfers, two-dimensional DMA, and
DMA chaining for automatic linked DMA transfers.
Multiprocessing
The ADSP-21160M offers powerful features tailored to
multiprocessing DSP systems as shown in Figure 4. The
external port and link ports provide integrated glueless mul-
tiprocessing support.
The external port supports a unified address space (see
Figure 2) that allows direct interprocessor accesses of each
ADSP-21160M’s internal memory. Distributed bus arbitra-
tion logic is included on-chip for simple, glueless connection
of systems containing up to six ADSP-21160Ms and a host
processor. Master processor changeover incurs only one
cycle of overhead. Bus arbitration is selectable as either fixed
or rotating priority. Bus lock allows indivisible read-mod-
ify-write sequences for semaphores. A vector interrupt is
provided for interprocessor commands. Maximum
throughput for interprocessor data transfer is 320M bytes/s
over the external port. Broadcast writes allow simultaneous
transmission of data to all ADSP-21160Ms and can be used
to implement reflective semaphores.
Six link ports provide for a second method of multiprocess-
ing communications. Each link port can support
communications to another ADSP-21160M. Using the
links, a large multiprocessor system can be constructed in a
2D or 3D fashion. Systems can use the link ports and cluster
multiprocessing concurrently or independently.
Link Ports
The ADSP-21160M features six 8-bit link ports that
provide additional I/O capabilities. With the capability of
running at 80 MHz rates, each link port can support 80M
bytes/s. Link port I/O is especially useful for point-to-point
interprocessor communication in multiprocessing systems.
The link ports can operate independently and simulta-
neously. Link port data is packed into 48- or 32-bit words,
and can be directly read by the core processor or
DMA-transferred to on-chip memory. Each link port has its
own double-buffered input and output registers.
Clock/acknowledge handshaking controls link port trans-
fers. Transfers are programmable as either transmit
or receive. For data throughput information, see link port
timing details in Table 18 on page 34.
Serial Ports
The ADSP-21160M features two synchronous serial ports
that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices. The serial ports
can operate up to half the clock rate of the core, providing
each with a maximum data rate of 40M bit/s. Independent
Figure 2. ADSP-21160M Memory Map
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Figure 3. ADSP-21160M External Data Alignment Options
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