參數(shù)資料
型號: ADSP-BF506BSWZ-4F
廠商: Analog Devices Inc
文件頁數(shù): 18/80頁
文件大?。?/td> 0K
描述: IC DSP 400MHZ 1.4V 120LQFP
視頻文件: Blackfin? BF50x Processor Family
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: 定點
接口: CAN,EBI/EMI,I²C,IrDA,PPI,SPI,SPORT,UART/USART
時鐘速率: 400MHz
非易失內(nèi)存: 閃存(16MB)
芯片上RAM: 68kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.29V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 120-LQFP-EP(14x14)
包裝: 托盤
Rev. A
|
Page 25 of 80
|
July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
PROCESSOR—SPECIFICATIONS
Specifications are subject to change without notice.
PROCESSOR—OPERATING CONDITIONS
Table 13 shows settings for TWI_DT in the NONGPIO_DRIVE
register. Set this register prior to using the TWI port.
Parameter
Conditions
Min
Nominal
Max
Unit
VDDINT
Internal Supply Voltage
Industrial Models
1.14
1.47
V
Internal Supply Voltage
Commercial Models
1.10
1.47
V
Internal Supply Voltage
Automotive Models
1.33
1.47
V
VDDEXT
1,2
1 Must remain powered (even if the associated function is not used).
2 1.8 V and 2.5 V I/O are supported only on ADSP-BF504 nonautomotive models. All ADSP-BF50x flash and automotive models support 3.3 V I/O only.
External Supply Voltage
1.8 V I/O, ADSP-BF504, Nonautomotive
and Non Flash Models
1.7
1.8
1.9
V
External Supply Voltage
2.5 V I/O, ADSP-BF504, Nonautomotive
and Non Flash Models
2.25
2.5
2.75
V
External Supply Voltage
3.3 V I/O, ADSP-BF50x, All Models
2.7
3.3
3.6
V
VDDFLASH
3 For ADSP-BF504, VDDFLASH pins should be connected to GND.
Flash Memory Supply Voltage
1.7
1.8
2.0
V
VIH
High Level Input Voltage4, 5
4 Bidirectional pins (PF15–0, PG15–0, PH2–0) and input pins (TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF50x processors are 3.3 V tolerant
(always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage.
5 Parameter value applies to all input and bidirectional pins, except SDA and SCL.
VDDEXT = 1.90 V
1.2
V
High Level Input Voltage4, 5
VDDEXT = 2.75 V
1.7
V
High Level Input Voltage4, 5
VDDEXT = 3.6 V
2.0
V
VIHTWI
High Level Input Voltage
6
6 Parameter applies to SDA and SCL.
VDDEXT = 1.90 V/2.75 V/3.6 V
0.7 × VBUSTWI
VBUSTWI
7, 8
7 The VIHTWI min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See VBUSTWI min and max values in Table 13.
V
VIL
Low Level Input Voltage
VDDEXT = 1.7 V
0.6
V
Low Level Input Voltage
VDDEXT = 2.25 V
0.7
V
Low Level Input Voltage4, 5
VDDEXT = 3.0 V
0.8
V
VILTWI
Low Level Input Voltage6
VDDEXT = minimum
0.3 × VBUSTWI
8
8 SDA and SCL are pulled up to VBUSTWI. See Table 13.
V
TJ
Junction Temperature
88-Lead LFCSP @ T
AMBIENT = –40°C to + 85°C
–40
+105
°C
Junction Temperature
88-Lead LFCSP @ T
AMBIENT = 0°C to + 70°C
0
+90
°C
Junction Temperature
120-Lead LQFP @ T
AMBIENT = –40°C to +85°C
–40
+105
°C
Junction Temperature
120-Lead LQFP @ T
AMBIENT = 0°C to +70°C
0
+90
°C
Junction Temperature
88-Lead LFCSP @ T
AMBIENT = –40°C to + 105°C –40
+125
°C
Table 13. TWI_DT Field Selections and VDDEXT/VBUSTWI
TWI_DT
VDDEXT Nominal
VBUSTWI Minimum
VBUSTWI Nominal
VBUSTWI Maximum
Unit
000 (default)
3.3
2.97
3.3
3.63
V
001
1.8
1.7
1.8
1.98
V
010
2.5
2.97
3.3
3.63
V
011
1.8
2.97
3.3
3.63
V
100
3.3
4.5
5
5.5
V
101
1.8
2.25
2.5
2.75
V
110
2.5
2.25
2.5
2.75
V
111 (reserved)
——
———
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