參數(shù)資料
型號(hào)： ADSP-BF506BSWZ-4F
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 57/80頁(yè)
文件大?。?/td> 0K
描述： IC DSP 400MHZ 1.4V 120LQFP
視頻文件： Blackfin? BF50x Processor Family
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： CAN，EBI/EMI，I²C，IrDA，PPI，SPI，SPORT，UART/USART
時(shí)鐘速率： 400MHz
非易失內(nèi)存： 閃存（16MB）
芯片上RAM： 68kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.29V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 120-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 120-LQFP-EP（14x14）
包裝： 托盤(pán)
Rev. A
|
Page 60 of 80
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July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
ADC—TERMINOLOGY
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the mea-
sured and the ideal 1 LSB change between any two adjacent
codes in the ADC.
Integral Nonlinearity (INL)
Integral nonlinearity is the maximum deviation from a
straight line passing through the endpoints of the ADC trans-
fer function. The endpoints of the transfer function are zero
scale with a single (1) LSB point below the first code transi-
tion, and full scale with a 1 LSB point above the last code
transition.
Offset Error
Offset error applies to straight binary output coding. It is the
deviation of the first code transition (00...000) to
(00 . . . 001) from the ideal (AGND + 1 LSB).
Offset Error Match
Offset error match is the difference in offset error across all 12
channels.
Gain Error
Gain error applies to straight binary output coding. It is the
deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (VREF 1 LSB) after the offset error
is adjusted out. Gain error does not include reference error.
Gain Error Match
Gain error match is the difference in gain error across all 12
channels.
Positive Gain Error
This applies when using twos complement output coding
with, for example, the 2 × VREF input range as –VREF to +VREF
biased about the VREF point. It is the deviation of the last code
transition (011…110) to (011…111) from the ideal
(+VREF – 1 LSB) after the zero code error is adjusted out.
Positive Gain Error Match
This is the difference in positive gain error across all 12
channels.
Zero Code Error
Zero code error applies when using twos complement output
coding with, for example, the 2 × VREF input range as –VREF to
+VREF biased about the VREF point. It is the deviation of the
mid-scale transition (all 0s to all 1s) from the ideal VIN voltage
(VREF).
Zero Code Error Match
Zero code error match refers to the difference in zero code
error across all 12 channels.
Negative Gain Error
This applies when using twos complement output coding
option, in particular the 2 × VREF input range as –VREF to
+VREF biased about the VREF point. It is the deviation of the
first code transition (100…000) to (100…001) from the ideal
(that is, –VREF + 1 LSB) after the zero code error is adjusted
out.
Negative Gain Error Match
This is the difference in negative gain error across all 12
channels.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode after the
end of conversion. Track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier
to reach its final value, within ±1/2 LSB, after the end of
conversion.
Signal-to-(Noise + Distortion) Ratio (SINAD)
This ratio is the measured ratio of signal-to-(noise + distor-
tion) at the output of the ADC. The signal is the rms
amplitude of the fundamental. Noise is the sum of all non-
fundamental signals up to half the sampling frequency (fS/2),
excluding dc. The ratio is dependent on the number of quan-
tization levels in the digitalization process; the more levels,
the smaller the quantization noise. The theoretical signal-to-
(noise + distortion) ratio for an ideal N-bit converter with a
sine wave input is given by:
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Therefore, for a 12-bit converter, theoretical SINAD is 74 dB.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of har-
monics to the fundamental. For the ADC, it is defined as:
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Effective Number of Bits (ENOB)
This is a figure of merit which characterizes the dynamic per-
formance of the ADC at a specified input frequency and
sampling rate. ENOB is expressed in bits. For a full scale sinu-
soidal input, ENOB is defined as:
ENOB = (SINAD – 1.76)/6.02
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic, or spurious noise, is defined as the ratio of
the rms value of the next largest component in the ADC out-
put spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is
a noise peak.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale (2 × VREF when VDD = 5 V, VREF when VDD = 3 V),
10 kHz sine wave signal to all un-selected input channels and
1
2
6
2
5
2
4
2
3
2
log
20
)
(
V
dB
THD
+
=
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參數(shù)描述
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ADSP-BF506F 制造商:Analog Devices 功能描述:LOW POWER BLACKFIN WITH ADVANCED EMBEDDED CONNECTIVITY - Bulk
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ADSP-BF506KSWZ-3F 功能描述:IC DSP 12BIT 300MHZ 120LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán)
ADSP-BF506KSWZ-4F 功能描述:IC DSP 12BIT 400MHZ 120LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán)
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