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參數(shù)資料
| 型號： | ADSP-BF506BSWZ-4F |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 45/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 400MHZ 1.4V 120LQFP |
| 視頻文件： | Blackfin? BF50x Processor Family |
| 標準包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點 |
| 接口： | CAN，EBI/EMI，I²C，IrDA，PPI，SPI，SPORT，UART/USART |
| 時鐘速率： | 400MHz |
| 非易失內存： | 閃存（16MB） |
| 芯片上RAM： | 68kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.29V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP 裸露焊盤 |
| 供應商設備封裝： | 120-LQFP-EP（14x14） |
| 包裝： | 托盤 |
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Rev. A
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Page 5 of 80
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July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The data memory holds data,
and a dedicated scratchpad data memory stores stack and local
variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The Blackfin processor views memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low latency core-accessible memory
as cache or SRAM and to provide larger, lower cost and perfor-
mance interface-accessible memory systems. See Figure 3.
The core-accessible L1 memory system is the highest perfor-
mance memory available to the Blackfin processor. The
interface-accessible memory system, accessed through the
external bus interface unit (EBIU), provides access to the inter-
nal flash memory and boot ROM.
The memory DMA controller provides high bandwidth data
movement capability. It can perform block transfers of code
or data between the internal memory and the external
memory spaces.
Internal (Core-Accessible) Memory
The processor has three blocks of core-accessible memory,
providing high-bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
32K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
The second core-accessible memory block is the L1 data mem-
ory, consisting of 32K bytes of SRAM, of which 16K bytes may
be configured as cache. This memory block is accessed at full
processor speed.
The third memory block is 4K bytes of scratchpad SRAM, which
runs at the same speed as the L1 memories, but this memory is
only accessible as data SRAM and cannot be configured as cache
memory.
External (Interface-Accessible) Memory
External memory is accessed via the EBIU memory port. This
16-bit interface provides a glueless connection to the internal
flash memory and boot ROM. Internal flash memory ships from
the factory in an erased state except for Block 0 of the parameter
bank. Block 0 of the Flash memory parameter bank ships from
the factory in an unknown state. An erase operation should be
performed prior to programming this block.
I/O Memory Space
The processor does not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory-mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks. One contains the control MMRs for all core functions,
and the other contains the registers needed for setup and con-
trol of the on-chip peripherals outside of the core. The MMRs
are accessible only in supervisor and emulation modes and
appear as reserved space to on-chip peripherals.
Figure 3. Internal/External Memory Map
INTERNAL
(CORE-A
CCESSIBLE)
MEMOR
Y
MAP
EXTERNAL
(INTERF
A
CE-A
CCESSIBLE)
MEMOR
Y
MAP
0x0000 0000
0x2000 0000
0x2040 0000
0xEF00 0000
0xEF00 1000
0xFF80 0000
0xFF80 4000
0xFF80 8000
0xFFA0 0000
0xFFA0 4000
0xFFA0 8000
0xFFA1 4000
0xFFB0 0000
0xFFB0 1000
0xFFC0 0000
0xFFE0 0000
0xFFFF FFFF
SYNC FLASH (32M BITS) *
RESERVED
BOOT ROM (4K BYTES)
L1 DATA BANK A SRAM (16K BYTES)
RESERVED
L1 DATA BANK A SRAM/CACHE (16K BYTES)
RESERVED
L1 INSTRUCTION SRAM/CACHE (16K BYTES)
RESERVED
L1 INSTRUCTION BANK A SRAM (16K BYTES)
RESERVED
INTERNAL SCRATCHPAD RAM (4K BYTES)
RESERVED
SYSTEM MEMORY MAPPED REGISTERS
CORE MEMORY MAPPED REGISTERS
* AVAILABLE ON PARTS WITH SYNC FLASH (F)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-BF506BSWZ-4FX | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-BF506F | 制造商:Analog Devices 功能描述:LOW POWER BLACKFIN WITH ADVANCED EMBEDDED CONNECTIVITY - Bulk |
| ADSPBF506FBSWZ-ENG | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-BF506KSWZ-3F | 功能描述:IC DSP 12BIT 300MHZ 120LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF506KSWZ-4F | 功能描述:IC DSP 12BIT 400MHZ 120LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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