參數(shù)資料
型號(hào)： ADSP-BF506BSWZ-4F
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 47/80頁(yè)
文件大?。?/td> 0K
描述： IC DSP 400MHZ 1.4V 120LQFP
視頻文件： Blackfin? BF50x Processor Family
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： CAN，EBI/EMI，I²C，IrDA，PPI，SPI，SPORT，UART/USART
時(shí)鐘速率： 400MHz
非易失內(nèi)存： 閃存（16MB）
芯片上RAM： 68kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.29V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 120-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 120-LQFP-EP（14x14）
包裝： 托盤
Rev. A
|
Page 51 of 80
|
July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time t
DIS is the
difference between t
DIS
_MEASURED and tDECAY as shown on the left side
The time for the voltage on the bus to decay by
ΔV is dependent
on the capacitive load C
L and the load current IL. This decay time
can be approximated by the equation:
The time t
DECAY is calculated with test loads CL and IL, and with
ΔV equal to 0.25 V for V
DDEXT (nominal) = 2.5 V/3.3 V and
0.15 V for VDDEXT (nominal) = 1.8 V.
The time t
DIS
_MEASURED is the interval from when the reference sig-
nal switches, to when the output voltage decays
ΔV from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY using the equation given above. Choose ΔV
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. C
L is
the total bus capacitance (per data line), and I
L is the total leak-
age or three-state current (per data line). The hold time will be
t
DECAY plus the various output disable times as specified in the
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 43). VLOAD is equal
to (VDDEXT) /2. The graphs of Figure 44 through Figure 49 show
how output rise time varies with capacitance. The delay and
hold specifications given should be derated by a factor derived
from these figures. The graphs in these figures may not be linear
outside the ranges shown.
Figure 43. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
tDIS
tDIS_MEASURED tDECAY
–
=
tDECAY
CL V
Δ
() I
L
=
T1
ZO = 50
: (impedance)
TD = 4.04
r 1.18 ns
2pF
TESTER PIN ELECTRONICS
50
:
0.5pF
70
:
400
:
45
:
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
VLOAD
DUT
OUTPUT
50
:
Figure 44. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8 V VDDEXT)
Figure 45. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5 V VDDEXT)
Figure 46. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3 V VDDEXT)
4
RISE
AND
F
ALL
TIME
(ns)
LOAD CAPACITANCE (pF)
0
50
100
150
250
9
7
0
1
3
6
200
t
RISE
t
FALL
t
RISE = 1.8V @ 25°C
t
FALL = 1.8V @ 25°C
2
5
8
4
RISE
AND
F
ALL
TIME
(ns)
LOAD CAPACITANCE (pF)
0
50
100
150
250
7
6
0
1
2
5
200
t
RISE
t
FALL
3
t
RISE = 2.5V @ 25°C
t
FALL = 2.5V @ 25°C
3
RISE
AND
F
ALL
TIME
(ns)
LOAD CAPACITANCE (pF)
0
50
100
150
250
6
5
0
1
2
4
200
t
RISE
t
FALL
t
RISE = 3.3V @ 25°C
t
FALL = 3.3V @ 25°C
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