參數(shù)資料
型號: ADSP-BF506BSWZ-4F
廠商: Analog Devices Inc
文件頁數(shù): 32/80頁
文件大小: 0K
描述: IC DSP 400MHZ 1.4V 120LQFP
視頻文件: Blackfin? BF50x Processor Family
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: 定點(diǎn)
接口: CAN,EBI/EMI,I²C,IrDA,PPI,SPI,SPORT,UART/USART
時鐘速率: 400MHz
非易失內(nèi)存: 閃存(16MB)
芯片上RAM: 68kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.29V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 120-LQFP-EP(14x14)
包裝: 托盤
Rev. A
|
Page 38 of 80
|
July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Serial Ports
through Figure 22 on Page 40 describe serial port operations.
Table 30. Serial Ports—External Clock
Parameter
V
DDEXT = 1.8 V
V
DDEXT = 2.5 V/3.3 V
Min
Max
Min
Max
Unit
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
3.0
ns
tHFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
3.0
ns
tSDRE
Receive Data Setup Before RSCLKx
3.0
ns
tHDRE
Receive Data Hold After RSCLKx1,2
3.5
3.0
ns
tSCLKEW
TSCLKx/RSCLKx Width
4.5
ns
tSCLKE
TSCLKx/RSCLKx Period
2 × tSCLK
ns
Switching Characteristics
tDFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)3
10.0
ns
tHOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)3
0.0
ns
tDDTE
Transmit Data Delay After TSCLKx3
11.0
10.0
ns
tHDTE
Transmit Data Hold After TSCLKx
0.0
ns
1 Referenced to sample edge.
2 When SPORT is used in conjunction with the ACM, refer to the timing requirements in Table 41 (ACM Timing).
3 Referenced to drive edge.
Table 31. Serial Ports—Internal Clock
Parameter
V
DDEXT = 1.8 V
V
DDEXT = 2.5 V/3.3 V
Min
Max
Min
Max
Unit
Timing Requirements
tSFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
11.0
9.6
ns
tHFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
–1.5
ns
tSDRI
Receive Data Setup Before RSCLKx1,2
11.5
10.0
ns
tHDRI
Receive Data Hold After RSCLKx1,2
–1.5
ns
Switching Characteristics
tSCLKIW
TSCLKx/RSCLKx Width
7.0
8.0
ns
tDFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)3
4.0
3.0
ns
tHOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)3
–2.0
–1.0
ns
tDDTI
Transmit Data Delay After TSCLKx3
4.0
3.0
ns
tHDTI
Transmit Data Hold After TSCLKx
–1.8
–1.5
ns
1 Referenced to sample edge.
2 When SPORT is used in conjunction with the ACM, refer to the timing requirements in Table 41 (ACM Timing).
3 Referenced to drive edge.
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