參數(shù)資料
型號(hào)： ADSP-BF506BSWZ-4F
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 78/80頁(yè)
文件大小： 0K
描述： IC DSP 400MHZ 1.4V 120LQFP
視頻文件： Blackfin? BF50x Processor Family
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： CAN，EBI/EMI，I²C，IrDA，PPI，SPI，SPORT，UART/USART
時(shí)鐘速率： 400MHz
非易失內(nèi)存： 閃存（16MB）
芯片上RAM： 68kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.29V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 120-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 120-LQFP-EP（14x14）
包裝： 托盤(pán)
Rev. A
|
Page 8 of 80
|
July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Event Control
The processor provides a very flexible mechanism to control the
processing of events. In the CEC, three registers are used to
coordinate and control events. Each register is 16 bits wide.
CEC interrupt latch register (ILAT)—Indicates when
events have been latched. The appropriate bit is set when
the processor has latched the event and is cleared when the
event has been accepted into the system. This register is
updated automatically by the controller, but it may be writ-
ten only when its corresponding IMASK bit is cleared.
CEC interrupt mask register (IMASK)—Controls the
masking and unmasking of individual events. When a bit is
set in the IMASK register, that event is unmasked and is
processed by the CEC when asserted. A cleared bit in the
IMASK register masks the event, preventing the processor
from servicing the event even though the event may be
latched in the ILAT register. This register may be read or
written while in supervisor mode. (Note that general-
purpose interrupts can be globally enabled and disabled
with the STI and CLI instructions, respectively.)
CEC interrupt pending register (IPEND)—The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
three pairs of 32-bit interrupt control and status registers. Each
register contains a bit, corresponding to each of the peripheral
interrupt events shown in Table 3 on Page 7.
SIC interrupt mask registers (SIC_IMASKx)—Control the
masking and unmasking of each peripheral interrupt event.
When a bit is set in these registers, the corresponding
peripheral event is unmasked and is forwarded to the CEC
when asserted. A cleared bit in these registers masks the
corresponding peripheral event, preventing the event from
propagating to the CEC.
SIC interrupt status registers (SIC_ISRx)—As multiple
peripherals can be mapped to a single event, these registers
allow the software to determine which peripheral event
source triggered the interrupt. A set bit indicates that the
peripheral is asserting the interrupt, and a cleared bit indi-
cates that the peripheral is not asserting the event.
SIC interrupt wakeup enable registers (SIC_IWRx)—By
enabling the corresponding bit in these registers, a periph-
eral can be configured to wake up the processor should the
core be idled or in sleep mode when the event is generated.
For more information, see Dynamic Power Management
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC recognizes and queues the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
MDMA Stream 1
IVG13
43
6
IAR5
IMASK1, ISR1, IWR1
Software Watchdog Timer
IVG13
44
6
IAR5
IMASK1, ISR1, IWR1
Port H Interrupt A
IVG13
45
6
IAR5
IMASK1, ISR1, IWR1
Port H Interrupt B
IVG13
46
6
IAR5
IMASK1, ISR1, IWR1
ACM Status Interrupt
IVG7
47
0
IAR5
IMASK1, ISR1, IWR1
ACM Interrupt
IVG10
48
3
IAR6
IMASK1, ISR1, IWR1
Reserved
—
49
—
IAR6
IMASK1, ISR1, IWR1
Reserved
—
50
—
IAR6
IMASK1, ISR1, IWR1
PWM0 Trip Interrupt
IVG10
51
3
IAR6
IMASK1, ISR1, IWR1
PWM0 Sync Interrupt
IVG10
52
3
IAR6
IMASK1, ISR1, IWR1
PWM1 Trip Interrupt
IVG10
53
3
IAR6
IMASK1, ISR1, IWR1
PWM1 Sync Interrupt
IVG10
54
3
IAR6
IMASK1, ISR1, IWR1
RSI Mask 1 Interrupt
IVG10
55
3
IAR6
IMASK1, ISR1, IWR1
Reserved
—
56 through 63
—
IMASK1, ISR1, IWR1
Table 3. System Interrupt Controller (SIC) (Continued)
Peripheral Interrupt Source
General-Purpose
Interrupt (at Reset)
Peripheral
Interrupt ID
Default Core
Interrupt ID
SIC Registers
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