參數(shù)資料
型號(hào)： ADSP-BF506BSWZ-4F
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 65/80頁(yè)
文件大?。?/td> 0K
描述： IC DSP 400MHZ 1.4V 120LQFP
視頻文件： Blackfin? BF50x Processor Family
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類(lèi)型： 定點(diǎn)
接口： CAN，EBI/EMI，I²C，IrDA，PPI，SPI，SPORT，UART/USART
時(shí)鐘速率： 400MHz
非易失內(nèi)存： 閃存（16MB）
芯片上RAM： 68kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.29V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 120-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 120-LQFP-EP（14x14）
包裝： 托盤(pán)
Rev. A
|
Page 68 of 80
|
July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
down for a relatively long duration between these bursts of sev-
eral conversions. When the ADC is in partial power-down, all
analog circuitry is powered down except for the on-chip refer-
ence and reference buffer.
To enter partial power-down mode, the conversion process
must be interrupted by bringing CS high anywhere after the sec-
ond falling edge of ADSCLK and before the 10th falling edge of
Mode). Once CS is brought high in this window of ADSCLKs,
the part enters partial power-down, the conversion that was ini-
tiated by the falling edge of CS is terminated, and DOUTA and
DOUTB go back into three-state. If CS is brought high before the
second ADSCLK falling edge, the part remains in normal mode
and does not power down. This avoids accidental power-down
due to glitches on the CS line.
To exit this mode of operation and power up the ADC again, a
dummy conversion is performed. On the falling edge of CS, the
device begins to power up and continues to power up as long as
CS is held low until after the falling edge of the 10th ADSCLK.
The device is fully powered up after approximately 1 μs has
elapsed, and valid data results from the next conversion, as
is brought high before the second falling edge of ADSCLK, the
ADC again goes into partial power-down. This avoids acciden-
tal power-up due to glitches on the CS line. Although the device
may begin to power up on the falling edge of CS, it powers down
again on the rising edge of CS. If the ADC is already in partial
power-down mode and CS is brought high between the second
and 10th falling edges of ADSCLK, the device enters full power-
down mode.
Full Power-Down Mode
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes substan-
tially longer than that from partial power-down. This mode is
more suited to applications where a series of conversions per-
formed at a relatively high throughput rate are followed by a
long period of inactivity and thus power-down. When the ADC
is in full power-down, all analog circuitry is powered down. Full
power-down is entered in a similar way as partial power-down,
except the timing sequence shown in Figure 81 (Entering Partial
Power-Down Mode) must be executed twice. The conversion
process must be interrupted in a similar fashion by bringing CS
high anywhere after the second falling edge of ADSCLK and
before the 10th falling edge of ADSCLK. The device enters par-
tial power-down at this point. To reach full power-down, the
next conversion cycle must be interrupted in the same way, as
CS is brought high in this window of ADSCLKs, the part com-
pletely powers down.
Note that it is not necessary to complete the 14 ADSCLKs once
CS is brought high to enter a power-down mode.
To exit full power-down and power up the ADC, a dummy con-
version is performed, as when powering up from partial power-
down. On the falling edge of CS, the device begins to power up
and continues to power up, as long as CS is held low until after
the falling edge of the 10th ADSCLK. The required power-up
time must elapse before a conversion can be initiated, as shown
Up Times section for the power-up times associated with the
ADC.
Figure 81. Entering Partial Power-Down Mode
ADSCLK
THREE-STATE
CS
DOUTA
DOUTB
114
10
2
Figure 82. Exiting Partial Power-Down Mode
ADSCLK
CS
DOUTA
DOUTB
INVALID DATA
VALID DATA
110
14
1
THE PART BEGINS
TO POWER UP.
THE PART IS FULLY
POWERED UP; SEE
POWER-UP TIMES
SECTION.
tPOWER-UP1
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參數(shù)描述
ADSP-BF506BSWZ-4FX 制造商:Analog Devices 功能描述:- Trays
ADSP-BF506F 制造商:Analog Devices 功能描述:LOW POWER BLACKFIN WITH ADVANCED EMBEDDED CONNECTIVITY - Bulk
ADSPBF506FBSWZ-ENG 制造商:Analog Devices 功能描述:- Trays
ADSP-BF506KSWZ-3F 功能描述:IC DSP 12BIT 300MHZ 120LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類(lèi)型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán)
ADSP-BF506KSWZ-4F 功能描述:IC DSP 12BIT 400MHZ 120LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類(lèi)型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán)
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