參數(shù)資料
型號： ADSP-TS203SABPZ050
廠商： Analog Devices Inc
文件頁數(shù)： 10/48頁
文件大?。?/td> 0K
描述： IC PROCESSOR 500MHZ 576BGA
標準包裝： 1
系列： TigerSHARC®
類型： 定點/浮點
接口： 主機接口，連接端口，多處理器
時鐘速率： 500MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 2.50V
電壓 - 核心： 1.05V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 576-BBGA 裸露焊盤
供應商設備封裝： 576-BGA-ED（25x25）
包裝： 托盤
Rev. D
|
Page 18 of 48
|
May 2012
STRAP PIN FUNCTION DESCRIPTIONS
Some pins have alternate functions at reset. Strap options set
processor operating modes. During reset, the processor samples
the strap option pins. Strap pins have an internal pull-up or
pull-down for the default value. If a strap pin is not connected to
an overdriving external pull-up, pull-down, or logic load, the
processor samples the default value during reset. If strap pins
are connected to logic inputs, a stronger external pull-up or
pull-down may be required to ensure default value depending
on leakage and/or low level input current of the logic load. To
set a mode other than the default mode, connect the strap pin to
a sufficiently stronger external pull-up or pull-down. Table 16
lists and describes each of the processor’s strap pins.
Table 15. Pin Definitions—Power, Ground, and Reference
Signal
Type
Term
Description
VDD
Pna
VDD pins for internal logic.
VDD_A
Pna
VDD pins for analog circuits. Pay critical attention to bypassing this supply.
VDD_IO
Pna
VDD pins for I/O buffers.
VDD_DRAM
Pna
VDD pins for internal DRAM.
VREF
I
na
Reference voltage defines the trip point for all input buffers, except SCLK, RST_IN,
POR_IN, IRQ3–0, FLAG3–0, DMAR3–0, ID2–0, CONTROLIMP1–0, LxDATO3–0P/N,
LxCLKOUTP/N, LxDATI3–0P/N, LxCLKINP/N, TCK, TDI, TMS, and TRST. VREF can be
connected to a power supply or set by a voltage divider circuit as shown in Figure 4.
SCLK_VREF
I
na
System Clock Reference. Connect this pin to a reference voltage as shown in
VSS
Gna
Ground pins.
NC
—
nc
No Connect. Do not connect these pins to anything (not to any supply, signal, or
each other). These pins are reserved and must be left unconnected.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up
approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect
directly to VSS
Table 16. Pin Definitions—I/O Strap Pins
Signal
Type (at
Reset)
On Pin …
Description
EBOOT
I (pd_0)
BMS
EPROM Boot.
0 = boot from EPROM immediately after reset (default)
1 = idle after reset and wait for an external device to boot processor through the
external port or a link port
IRQEN
I (pd)
BM
Interrupt Enable.
0 = disable and set IRQ3–0 interrupts to edge-sensitive after reset (default)
1 = enable and set IRQ3–0 interrupts to level-sensitive immediately after reset
LINK_DWIDTH
I (pd)
TMR0E
Link Port Input Default Data Width.
0 = 1-bit (default)
1 = 4-bit
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
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