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參數(shù)資料
| 型號： | ADSP-TS203SABPZ050 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/48頁 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR 500MHZ 576BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TigerSHARC® |
| 類型： | 定點/浮點 |
| 接口： | 主機接口，連接端口，多處理器 |
| 時鐘速率： | 500MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 2.50V |
| 電壓 - 核心： | 1.05V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 576-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 576-BGA-ED（25x25） |
| 包裝： | 托盤 |
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Rev. D
|
Page 5 of 48
|
May 2012
Interrupt Controller
The processor supports nested and nonnested interrupts. Each
interrupt type has a register in the interrupt vector table. Also,
each has a bit in both the interrupt latch register and the inter-
rupt mask register. All interrupts are fixed as either level-
sensitive or edge-sensitive, except the IRQ3–0 hardware inter-
rupts, which are programmable.
The processor distinguishes between hardware interrupts and
software exceptions, handling them differently. When a soft-
ware exception occurs, the processor aborts all other
instructions in the instruction pipe. When a hardware interrupt
occurs, the processor continues to execute instructions already
in the instruction pipe.
Flexible Instruction Set
The 128-bit instruction line, which can contain up to four 32-bit
instructions, accommodates a variety of parallel operations for
concise programming. For example, one instruction line can
direct the processor to conditionally execute a multiply, an add,
and a subtract in both computation blocks while it also branches
to another location in the program. Some key features of the
instruction set include:
Algebraic assembly language syntax
Direct support for all DSP, imaging, and video arithmetic
types
Eliminates toggling hardware modes because modes are
supported as options (for example, rounding, saturation,
and others) within instructions
Branch prediction encoded in instruction; enables zero-
overhead loops
Parallelism encoded in instruction line
Conditional execution optional for all instructions
User-defined partitioning between program and data
memory
MEMORY
The processor’s internal and external memory is organized into
a unified memory map, which defines the location (address) of
all elements in the system, as shown in Figure 2.
The memory map is divided into four memory areas—host
space, external memory, multiprocessor space, and internal
memory—and each memory space, except host memory, is sub-
divided into smaller memory spaces.
The ADSP-TS203S processor internal memory has 4M bits of
on-chip DRAM memory, divided into four blocks of 1M bits
(32K words
× 32 bits). Each block—M0, M2, M4, and M6—can
store program instructions, data, or both, so applications can
configure memory to suit specific needs. Placing program
instructions and data in different memory blocks, however,
enables the processor to access data while performing an
instruction fetch. Each memory segment contains a 128K bit
cache to enable single-cycle accesses to internal DRAM.
The four internal memory blocks connect to the four 128-bit
wide internal buses through a crossbar connection, enabling the
processor to perform four memory transfers in the same cycle.
The processor’s internal bus architecture provides a total mem-
ory bandwidth of 28G bytes per second, allowing the core and
I/O to access eight 32-bit data-words and four 32-bit instruc-
tions each cycle. Additional features are:
Processor core and I/O access to different memory blocks
in the same cycle
Processor core access to three memory blocks in parallel—
one instruction and two data accesses
Programmable partitioning of program and data memory
Program access of all memory as 32-, 64-, or 128-bit
words—16-bit words with the DAB
EXTERNAL PORT (OFF-CHIP
MEMORY/PERIPHERALS INTERFACE)
The ADSP-TS203S processor’s external port provides the pro-
cessor’s interface to off-chip memory and peripherals. The
4G word address space is included in the processor’s unified
address space. The separate on-chip buses—four 128-bit data
buses and four 32-bit address buses—are multiplexed at the
SOC interface and transferred to the external port over the SOC
bus to create an external system bus transaction. The external
system bus provides a single 32-bit data bus and a single 32-bit
address bus. The external port supports data transfer rates of
500M bytes per second over the external bus.
The external bus is configured for 32-bit, little-endian opera-
tions. Unlike the ADSP-TS201, the ADSP-TS203S processor’s
external port cannot support 64-bit operations; the external bus
width control bits (Bits 21-19) must = 0 in the SYSCON regis-
ter—all other values are illegal for the ADSP-TS203S. Because
the external port is restricted to 32 bits on the ADSP-TS203S
processor, there are a number of pinout differences between the
ADSP-TS203S and the ADSP-TS201 processors.
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory-
mapped peripherals is facilitated by on-chip decoding of high
order address lines to generate memory bank select signals.
The ADSP-TS203S processor provides programmable memory,
pipeline depth, and idle cycle for synchronous accesses, and
external acknowledge controls to interface to pipelined or slow
devices, host processors, and other memory-mapped peripher-
als with variable access, hold, and disable time requirements.
Host Interface
The ADSP-TS203S processor provides an easy and configurable
interface between its external bus and host processors through
the external port. To accommodate a variety of host processors,
the host interface supports pipelined or slow protocols for pro-
cessor access of the host as slave or pipelined for host access of
the ADSP-TS203S processor as slave. Each protocol has pro-
grammable transmission parameters, such as idle cycles, pipe
depth, and internal wait cycles.
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