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| 型號： | ADSP-TS203SABPZ050 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR 500MHZ 576BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TigerSHARC® |
| 類型： | 定點/浮點 |
| 接口： | 主機接口，連接端口，多處理器 |
| 時鐘速率： | 500MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 2.50V |
| 電壓 - 核心： | 1.05V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 576-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 576-BGA-ED（25x25） |
| 包裝： | 托盤 |
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Rev. D
|
Page 12 of 48
|
May 2012
Table 5. Pin Definitions—External Port Bus Controls
Signal
Type
Term
Description
ADDR31–0
I/O/T
(pu_ad)
nc
Address Bus. The processor issues addresses for accessing memory and peripherals
on these pins. In a multiprocessor system, the bus master drives addresses for
accessing internal memory or I/O processor registers of other ADSP-TS203S
processors. The processor inputs addresses when a host or another processor
accesses its internal memory or I/O processor registers.
DATA31–0
I/O/T
(pu_ad)
nc
External Data Bus. The processor drives and receives data and instructions on these
pins. Pull-up or pull-down resistors on unused DATA pins are unnecessary.
RD
I/O/T
(pu_0)
epu1
Memory Read. RD is asserted whenever the processor reads from any slave in the
system, excluding SDRAM. When the processor is a slave, RD is an input and
indicates read transactions that access its internal memory or universal registers. In
a multiprocessor system, the bus master drives RD. RD changes concurrently with
ADDR pins.
WRL
I/O/T
(pu_0)
epu1
Write Low. WRL is asserted when the ADSP-TS203S processor writes to the external
bus (host, memory, or processor). An external master (host or processor) asserts WRL
for writing to a processor’s internal memory. In a multiprocessor system, the bus
master drives WRL. WRL changes concurrently with ADDR pins. When the processor
is a slave, WRL is an input and indicates write transactions that access its internal
memory or universal registers.
ACK
I/O/T/OD
(pu_od_0)
epu1
Acknowledge. External slave devices can deassert ACK to add wait states to external
memory accesses. ACK is used by I/O devices, memory controllers, and other periph-
erals on the data phase. The processor can deassert ACK to add wait states to read
and write accesses of its internal memory. The pull-up is 50 Ω on low-to-high trans-
actions and is 500 Ω on all other transactions.
BMS
O/T
(pu_0)
na
Boot Memory Select. BMS is the chip select for boot EPROM or flash memory. During
reset, the processor uses BMS as a strap pin (EBOOT) for EPROM boot mode. In a
multiprocessor system, the processor bus master drives BMS. For details, see Reset
and Booting on Page 8 and the EBOOT signal description in Table 16 on Page 18.
MS1–0
O/T
(pu_0)
nc
Memory Select. MS0 or MS1 is asserted whenever the processor accesses memory
banks 0 or 1, respectively. MS1–0 are decoded memory address pins that change
concurrently with ADDR pins. When ADDR31:27 = 0b00110, MS0 is asserted. When
ADDR31:27 = 0b00111, MS1 is asserted. In multiprocessor systems, the master
processor drives MS1–0.
MSH
O/T
(pu_0)
nc
Memory Select Host. MSH is asserted whenever the processor accesses the host
address space (ADDR31 = 0b1). MSH is a decoded memory address pin that changes
concurrently with ADDR pins. In a multiprocessor system, the bus master processor
drives MSH.
BRST
I/O/T
(pu_0)
Burst. The current bus master (processor or host) asserts this pin to indicate that it
is reading or writing data associated with consecutive addresses. A slave device can
ignore addresses after the first one and increment an internal address counter after
each transfer. For host-to-processor burst accesses, the processor increments the
address automatically while BRST is asserted.
TM4
I/O/T
epu
Test Mode 4. Must be pulled up to VDD_IO with a 5 kΩ resistor.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up
approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect
directly to VSS
1 This external pull-up may be omitted for the ID = 000 TigerSHARC processor.
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