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| 型號： | ADSP-TS203SABPZ050 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR 500MHZ 576BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TigerSHARC® |
| 類型： | 定點/浮點 |
| 接口： | 主機接口，連接端口，多處理器 |
| 時鐘速率： | 500MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 2.50V |
| 電壓 - 核心： | 1.05V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 576-BBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 576-BGA-ED（25x25） |
| 包裝： | 托盤 |
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Rev. D
|
Page 11 of 48
|
May 2012
PIN FUNCTION DESCRIPTIONS
While most of the ADSP-TS203S processor’s input pins are nor-
mally synchronous—tied to a specific clock—a few are
asynchronous. For these asynchronous signals, an on-chip syn-
chronization circuit prevents metastability problems. Use the ac
specification for asynchronous signals when the system design
requires predictable, cycle-by-cycle behavior for these signals.
The output pins can be three-stated during normal operation.
The processor three-states all output during reset, allowing
these pins to get to their internal pull-up or pull-down state.
Some pins have an internal pull-up or pull-down resistor (±30%
tolerance) that maintains a known value during transitions
between different drivers.
Table 3. Pin Definitions—Clocks and Reset
Signal
Type
Term
Description
SCLKRAT2–0
I (pd)
na
Core Clock Ratio. The processor’s core clock (CCLK) rate = n
× SCLK, where n is user-
programmable using the SCLKRATx pins to the values shown in Table 4. These pins
may change only during reset; connect these pins to VDD_IO or VSS. All reset specifi-
(CCLK) is the instruction cycle rate.
SCLK
I
na
System Clock Input. The processor’s system input clock for cluster bus. The core
clock rate is user-programmable using the SCLKRATx pins. For more information,
RST_IN
I/A
na
Reset. Sets the processor to a known state and causes program to be in idle state.
RST_IN must be asserted a specified time according to the type of reset operation.
RST_OUT
O
na
Reset Output. Indicates that the processor reset is complete. Connect to POR_IN.
POR_IN
I/A
na
Power-On Reset for internal DRAM. Connect to RST_OUT.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up
approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect
directly to VSS
Table 4. SCLK Ratio
SCLKRAT2–0
Ratio
000
(default)
4
001
5
010
6
011
7
100
8
101
10
110
12
111
Reserved
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-TS203SBBPZ050 | 制造商:Analog Devices 功能描述:DSP - Bulk |
| ADSQ-1410 | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-C | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-EX-C | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410S | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 0 to 70C 66-pin DIP Quad 14-Bit, 10MPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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