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參數(shù)資料
| 型號： | ADSP-TS203SABPZ050 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR 500MHZ 576BGA |
| 標準包裝： | 1 |
| 系列： | TigerSHARC® |
| 類型： | 定點/浮點 |
| 接口： | 主機接口，連接端口，多處理器 |
| 時鐘速率： | 500MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 2.50V |
| 電壓 - 核心： | 1.05V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 576-BBGA 裸露焊盤 |
| 供應商設備封裝： | 576-BGA-ED（25x25） |
| 包裝： | 托盤 |
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Rev. D
|
Page 16 of 48
|
May 2012
Table 10. Pin Definitions—Flags, Interrupts, and Timer
Signal
Type
Term
Description
FLAG3–0
I/O/A
(pu)
nc
FLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin
can be configured individually for input or for output. FLAG3–0 are inputs after power-
up and reset.
IRQ3–0
I/A
(pu)
nc
Interrupt Request. When asserted, the processor generates an interrupt. Each of the
IRQ3–0 pins can be independently set for edge-triggered or level-sensitive operation.
After reset, these pins are disabled unless the IRQ3–0 strap option and interrupt vectors
are initialized for booting.
TMR0E
O
na
Timer 0 expires. This output pulses whenever timer 0 expires. At reset, this is a strap pin.
For more information, see Table 16 on Page 18.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up
approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect
directly to VSS
Table 11. Pin Definitions—Link Ports
Signal
Type
Term
Description
LxDATO3–0P
O
nc
Link Ports 1–0 Data 1–0 Transmit LVDS P
LxDATO3–0N
O
nc
Link Ports 1–0 Data 1–0 Transmit LVDS N
LxCLKOUTP
O
nc
Link Ports 1–0 Transmit Clock LVDS P
LxCLKOUTN
O
nc
Link Ports 1–0 Transmit Clock LVDS N
LxACKI
I (pd)
nc
Link Ports 1–0 Receive Acknowledge. Using this signal, the receiver indicates to the
transmitter that it may continue the transmission.
LxBCMPO
O (pu)
nc
Link Ports 1–0 Block Completion. When the transmission is executed using DMA,
this signal indicates to the receiver that the transmitted block is completed. The
pull-up resistor is present on L0BCMPO only. At reset, the L1BCMPO pin is a strap
pin. For more information, see Table 16 on Page 18.
LxDATI3–0P
I
VDD_IO
Link Ports 1–0 Data 3–0 Receive LVDS P
LxDATI3–0N
I
VDD_IO
Link Ports 1–0 Data 3–0 Receive LVDS N
LxCLKINP
I/A
VDD_IO
Link Ports 1–0 Receive Clock LVDS P
LxCLKINN
I/A
VDD_IO
Link Ports 1–0 Receive Clock LVDS N
LxACKO
O
nc
Link Ports 1–0 Transmit Acknowledge. Using this signal, the receiver indicates to the
transmitter that it may continue the transmission.
LxBCMPI
I (pd_l)
VSS
Link Ports 1–0 Block Completion. When the reception is executed using DMA, this
signal indicates to the receiver that the transmitted block is completed.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up
approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect
directly to VSS
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相關代理商/技術參數(shù) |
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|---|---|
| ADSP-TS203SBBPZ050 | 制造商:Analog Devices 功能描述:DSP - Bulk |
| ADSQ-1410 | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
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| ADSQ-1410S | 功能描述:模數(shù)轉換器 - ADC 0 to 70C 66-pin DIP Quad 14-Bit, 10MPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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