參數(shù)資料
型號： ADSP-TS203SABPZ050
廠商： Analog Devices Inc
文件頁數(shù)： 6/48頁
文件大小： 0K
描述： IC PROCESSOR 500MHZ 576BGA
標準包裝： 1
系列： TigerSHARC®
類型： 定點/浮點
接口： 主機接口，連接端口，多處理器
時鐘速率： 500MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 2.50V
電壓 - 核心： 1.05V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 576-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 576-BGA-ED（25x25）
包裝： 托盤
Rev. D
|
Page 14 of 48
|
May 2012
Table 7. Pin Definitions—External Port DMA/Flyby
Signal
Type
Term
Description
DMAR3–0
I/A
epu
DMA Request Pins. Enable external I/O devices to request DMA services from the
processor. In response to DMARx, the processor performs DMA transfers according
to the DMA channel’s initialization. The processor ignores DMA requests from unini-
tialized channels.
IOWR
O/T
(pu_0)
nc
I/O Write. When a processor DMA channel initiates a flyby mode read transaction,
the processor asserts the IOWR signal during the data cycles. This assertion makes
the I/O device sample the data instead of the TigerSHARC.
IORD
O/T
(pu_0)
nc
I/O Read. When a processor DMA channel initiates a flyby mode write transaction,
the processor asserts the IORD signal during the data cycle. This assertion with the
IOEN makes the I/O device drive the data instead of the TigerSHARC.
IOEN
O/T
(pu_0)
nc
I/O Device Output Enable. Enables the output buffers of an external I/O device for
fly-by transactions between the device and external memory. Active on flyby
transactions.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up
approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect
directly to VSS
Table 8. Pin Definitions—External Port SDRAM Controller
Signal
Type
Term
Description
MSSD3–0
I/O/T
(pu_0)
nc
Memory Select SDRAM. MSSD0, MSSD1, MSSD2, or MSSD3 is asserted whenever the
processor accesses SDRAM memory space. MSSD3–0 are decoded memory address
pins that are asserted whenever the processor issues an SDRAM command cycle
(access to ADDR31:30 = 0b01—except reserved spaces shown in Figure 2 on
Page 6). In a multiprocessor system, the master processor drives MSSD3–0.
RAS
I/O/T
(pu_0)
nc
Row Address Select. When sampled low, RAS indicates that a row address is valid in
a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation
to execute according to SDRAM specification.
CAS
I/O/T
(pu_0)
nc
Column Address Select. When sampled low, CAS indicates that a column address is
valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of
operation to execute according to the SDRAM specification.
LDQM
O/T
(pu_0)
nc
Low Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ
buffers. LDQM is valid on SDRAM transactions when CAS is asserted, and inactive
on read transactions.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up
approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect
directly to VSS
相關(guān)PDF資料
PDF描述
ASM25DTBD CONN EDGECARD 50POS R/A .156 SLD
ADSP-21160NKBZ-100 IC DSP CONTROLLER 32BIT 400-BGA
ADSP-21062LCSZ-160 IC DSP CONTROLLER 32BIT 240MQFP
AGM25DTBD CONN EDGECARD 50POS R/A .156 SLD
AYM25DTAN CONN EDGECARD 50POS R/A .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-TS203SBBPZ050 制造商:Analog Devices 功能描述:DSP - Bulk
ADSQ-1410 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter
ADSQ-1410-C 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter
ADSQ-1410-EX-C 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter
ADSQ-1410S 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 0 to 70C 66-pin DIP Quad 14-Bit, 10MPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*