參數(shù)資料
型號(hào)： ADSP-TS203SABPZ050
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/48頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR 500MHZ 576BGA
標(biāo)準(zhǔn)包裝： 1
系列： TigerSHARC®
類型： 定點(diǎn)/浮點(diǎn)
接口： 主機(jī)接口，連接端口，多處理器
時(shí)鐘速率： 500MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 2.50V
電壓 - 核心： 1.05V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 576-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 576-BGA-ED（25x25）
包裝： 托盤
Rev. D
|
Page 15 of 48
|
May 2012
SDA10
O/T
(pu_0)
nc
SDRAM Address Bit 10. Separate A10 signals enable SDRAM refresh operation while
the processor executes non-SDRAM transactions.
SDCKE
I/O/T
(pu_m/
pd_m)
nc
SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend
modes. A slave processor in a multiprocessor system does not have the pull-up or
pull-down. A master processor (or ID = 0 in a single processor system) has a pull-up
before granting the bus to the host, except when the SDRAM is put in self refresh
mode. In self refresh mode, the master has a pull-down before granting the bus to
the host.
SDWE
I/O/T
(pu_0)
nc
SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an
SDRAM write access. When sampled high while CAS is active, SDWE indicates an
SDRAM read access. In other SDRAM accesses, SDWE defines the type of operation
to execute according to SDRAM specification.
Table 9. Pin Definitions—JTAG Port
Signal
Type
Term
Description
EMU
O/OD
nc1
Emulation. Connected to the processor’s JTAG emulator target board connector
only.
TCK
I
epd or epu1
Test Clock (JTAG). Provides an asynchronous clock for JTAG scan.
TDI
I
(pu_ad)
Test Data Input (JTAG). A serial data input of the scan path.
TDO
O/T
Test Data Output (JTAG). A serial data output of the scan path.
TMS
I
(pu_ad)
Test Mode Select (JTAG). Used to control the test state machine.
TRST
I/A
(pu_ad)
na
Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed
low after power-up for proper device operation. For more information, see Reset
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up
approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect
directly to VSS
1 See the reference on Page 10 to the JTAG emulation technical reference EE-68.
Table 8. Pin Definitions—External Port SDRAM Controller (Continued)
Signal
Type
Term
Description
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5kΩ; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on processor ID = 0; pu_0 = internal pull-up 5 kΩ on processor ID = 0;
pu_od_0 = internal pull-up 500 Ω on processor ID = 0; pd_m = internal pull-down 5 kΩ on processor bus master; pu_m = internal pull-up
5 kΩ on processor bus master; pu_ad = internal pull-up 40 kΩ. For more pull-down and pull-up information, see Electrical Characteristics
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 kΩ to VSS; epu = external pull-up
approximately 5 kΩ to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect
directly to VSS
相關(guān)PDF資料
PDF描述
ASM25DTBD CONN EDGECARD 50POS R/A .156 SLD
ADSP-21160NKBZ-100 IC DSP CONTROLLER 32BIT 400-BGA
ADSP-21062LCSZ-160 IC DSP CONTROLLER 32BIT 240MQFP
AGM25DTBD CONN EDGECARD 50POS R/A .156 SLD
AYM25DTAN CONN EDGECARD 50POS R/A .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-TS203SBBPZ050 制造商:Analog Devices 功能描述:DSP - Bulk
ADSQ-1410 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter
ADSQ-1410-C 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter
ADSQ-1410-EX-C 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter
ADSQ-1410S 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 0 to 70C 66-pin DIP Quad 14-Bit, 10MPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*