參數資料
型號： ADSP-TS203SABPZ050
廠商： Analog Devices Inc
文件頁數： 30/48頁
文件大小： 0K
描述： IC PROCESSOR 500MHZ 576BGA
標準包裝： 1
系列： TigerSHARC®
類型： 定點/浮點
接口： 主機接口，連接端口，多處理器
時鐘速率： 500MHz
非易失內存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 2.50V
電壓 - 核心： 1.05V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 576-BBGA 裸露焊盤
供應商設備封裝： 576-BGA-ED（25x25）
包裝： 托盤
Rev. D
|
Page 36 of 48
|
May 2012
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The time for the voltage on the bus to ramp by ΔV is
dependent on the capacitive load, CL, and the drive current, ID.
This ramp time can be approximated by the following equation:
The output enable time tENA is the difference between
tMEASURED_ENA and tRAMP as shown in Figure 33. The time
tMEASURED_ENA is the interval from when the reference signal
switches to when the output voltage ramps ΔV from the mea-
sured three-stated output level. tRAMP is calculated with test load
CL, drive current ID, and with ΔV equal to 0.4 V.
Capacitive Loading
Output valid and hold are based on standard capacitive loads:
30 pF on all pins (see Figure 34). The delay and hold specifica-
tions given should be derated by a drive strength related factor
for loads other than the nominal value of 30 pF. Figure 35
through Figure 42 show how output rise time varies with capac-
itance. Figure 43 graphically shows how output valid varies with
load capacitance. (Note that this graph or derating does not
apply to output disable delays; see Output Disable Time on
Page 35.) The graphs of Figure 35 through Figure 43 may not be
linear outside the ranges shown.
Figure 33. Output Enable/Disable
Figure 34. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS
DRIVING
VOH (MEASURED) – DV
VOL (MEASURED) + DV
tMEASURED_DIS
VOH (MEASURED)
VOL (MEASURED)
1.65V
0.85V
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.25V.
OUTPUT STOPS
DRIVING
tDECAY
tENA
tMEASURED_ENA
tRAMP
tRAMP
CL V
Δ
() I
D
=
1.25V
TO
OUTPUT
PIN
30pF
50
V
Figure 35. Typical Output Rise and Fall Time (10% to 90%, VDD_IO =2.5 V)
vs. Load Capacitance at Strength 0
Figure 36. Typical Output Rise and Fall Time (10% to 90%, VDD_IO =2.5 V)
vs. Load Capacitance at Strength 1
0
10
20
30
40
50
60
70
80
90
100
0
5
10
15
20
25
RISE TIME
Y = 0.259x + 3.0842
STRENGTH 0
(VDD_IO =2.5V)
R
IS
E
A
N
D
F
A
L
T
IM
E
S
(n
s
)
LOAD CAPACITANCE (pF)
FALL TIME
Y = 0.251x + 4.2245
0
10
20
30
405060
70
80
90
100
0
5
10
15
20
25
R
IS
E
A
N
D
F
A
L
T
IM
E
S
(n
s
)
LOAD CAPACITANCE (pF)
STRENGTH 1
(VDD_IO =2.5V)
RISE TIME
Y = 0.1501
x +0.05
FALL TIME
Y = 0.1527x + 0.7485
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