參數(shù)資料
型號(hào): ADSP-TS203SABPZ050
廠商: Analog Devices Inc
文件頁(yè)數(shù): 17/48頁(yè)
文件大小: 0K
描述: IC PROCESSOR 500MHZ 576BGA
標(biāo)準(zhǔn)包裝: 1
系列: TigerSHARC®
類型: 定點(diǎn)/浮點(diǎn)
接口: 主機(jī)接口,連接端口,多處理器
時(shí)鐘速率: 500MHz
非易失內(nèi)存: 外部
芯片上RAM: 512kB
電壓 - 輸入/輸出: 2.50V
電壓 - 核心: 1.05V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 576-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 576-BGA-ED(25x25)
包裝: 托盤
Rev. D
|
Page 24 of 48
|
May 2012
Table 23. Reference Clocks—System Clock (SCLK) Cycle Time
Parameter
Description
SCLKRAT = 4×, 6×, 8×, 10×, 12×
SCLKRAT = 5×, 7×
Unit
Min
Max
Min
Max
tSCLK
1, 2, 3
System Clock Cycle Time
8
50
8
50
ns
tSCLKH
System Clock Cycle High Time
0.40 × tSCLK
0.60 × tSCLK
0.45 × tSCLK
0.55 × tSCLK
ns
tSCLKL
System Clock Cycle Low Time
0.40 × tSCLK
0.60 × tSCLK
0.45 × tSCLK
0.55 × tSCLK
ns
tSCLKF
System Clock Transition Time—Falling Edge4
1.5
ns
tSCLKR
System Clock Transition Time—Rising Edge
1.5
ns
tSCLKJ
5, 6
System Clock Jitter Tolerance
500
ps
1 For more information, see Table 3 on Page 11.
3 The value of (tSCLK / SCLKRAT2-0) must not violate the specification for tCCLK.
4 System clock transition times apply to minimum SCLK cycle time (tSCLK) only.
5 Actual input jitter should be combined with ac specifications for accurate timing analysis.
6 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
Figure 8. Reference Clocks—System Clock (SCLK) Cycle Time
Table 24. Reference Clocks—JTAG Test Clock (TCK) Cycle Time
Parameter
Description
Min
Max
Unit
tTCK
Test Clock (JTAG) Cycle Time
Greater of 30 or tCCLK × 4
ns
tTCKH
Test Clock (JTAG) Cycle High Time
12
ns
tTCKL
Test Clock (JTAG) Cycle Low Time
12
ns
Figure 9. Reference Clocks—JTAG Test Clock (TCK) Cycle Time
SCLK
tSCLK
tSCLKH
tSCLKL
tSCLKJ
tSCLKF
tSCLKR
TCK
tTCK
tTCKH
tTCKL
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