- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1908 > COP8CCR9KMT8 (National Semiconductor)IC MCU EEPROM 8BIT 32K 56-TSSOP PDF資料下載
參數(shù)資料
| 型號： | COP8CCR9KMT8 |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 87/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU EEPROM 8BIT 32K 56-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 34 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 49 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 包裝： | 管件 |
| 其它名稱： | *COP8CCR9KMT8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁當(dāng)前第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
To ensure reliable operation, the user should always use the VIS instruction to determine the source of an
interrupt. Although it is possible to poll the pending bits to detect the source of an interrupt, this practice is
not recommended. The use of polling allows the standard arbitration ranking to be altered, but the
reliability of the interrupt system is compromised. The polling routine must individually test the enable and
pending bits of each maskable interrupt. If a Software Trap interrupt should occur, it will be serviced last,
even though it should have the highest priority. Under certain conditions, a Software Trap could be
triggered but not serviced, resulting in an inadvertent “l(fā)ocking out” of all maskable interrupts by the
Software Trap pending flag. Problems such as this can be avoided by using VIS instruction.
Table 5-25. Interrupt Vector Table
Arbitration
Vector Address(1)
Source Description
Ranking
(Hi-Low Byte)
(1) Highest
Software
INTR Instruction
0yFE–0yFF
(2)
Reserved for NMI
0yFC–0yFD
(3)
External
G0
0yFA–0yFB
(4)
Timer T0
Underflow
0yF8–0yF9
(5)
Timer T1
T1A/Underflow
0yF6–0yF7
(6)
Timer T1
T1B
0yF4–0yF5
(7)
MICROWIRE/PLUS
BUSY Low
0yF2–0yF3
(8)
Reserved
0yF0–0yF1
(9)
USART
Receive
0yEE–0yEF
(10)
USART
Transmit
0yEC–0yED
(11)
Timer T2
T2A/Underflow
0yEA–0yEB
(12)
Timer T2
T2B
0yE8–0yE9
(13)
Timer T3
T3A/Underflow
0yE6–0yE7
(14)
Timer T3
T3B
0yE4–0yE5
(15)
Port L/Wake-up
Port L Edge
0yE2–0yE3
(16) Lowest
Default VIS
Reserved
0yE0–0yE1
(1)
y is a variable which represents the VIS block. VIS and the vector table must be located in the same
256-byte block except if VIS is located at the last address of a block. In this case, the table must be in
the next block.
5.15.3.1 VIS Execution
When the VIS instruction is executed it activates the arbitration logic. The arbitration logic generates an
even number between E0 and FE (E0, E2, E4, E6 etc....) depending on which active interrupt has the
highest arbitration ranking at the time of the 1st cycle of VIS is executed. For example, if the software trap
interrupt is active, FE is generated. If the external interrupt is active and the software trap interrupt is not,
then FA is generated and so forth. If no active interrupt is pending, than E0 is generated. This number
replaces the lower byte of the PC. The upper byte of the PC remains unchanged. The new PC is therefore
pointing to the vector of the active interrupt with the highest arbitration ranking. This vector is read from
program memory and placed into the PC which is now pointed to the 1st instruction of the service routine
of the active interrupt with the highest arbitration ranking.
Figure 5-24 illustrates the different steps performed by the VIS instruction. Figure 5-25 shows a flowchart
for the VIS instruction.
The non-maskable interrupt pending flag is cleared by the RPND (Reset Non-Maskable Pending Bit)
instruction (under certain conditions) and upon RESET.
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
77
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| COP8SAA716M8/NOPB | IC MCU OTP 8BIT 1K 16-SOIC |
| CP2101-GMR | IC CTRLR BRIDGE USB-UART 28MLP |
| CP2103-GMR | IC CTRLR BRIDGE USB-UART 28MLP |
| CP2104-F03-GM | IC SGL USB-TO-UART BRIDGE 24QFN |
| CP2105-F01-GM | IC SGL USB-DL UART BRIDGE 24QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| COP8CCR9LVA7 | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| COP8CCR9LVA7/63 | 制造商:Texas Instruments 功能描述: |
| COP8CCR9LVA7/63SN | 功能描述:閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| COP8CCR9LVA7/NOPB | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| COP8CCR9LVA763SN | 制造商:National Semiconductor 功能描述:MCU 8-bit COP8 CISC 32KB Flash 5V 68-Pin PLCC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。