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參數(shù)資料
| 型號： | COP8CCR9KMT8 |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 94/111頁 |
| 文件大小： | 0K |
| 描述： | IC MCU EEPROM 8BIT 32K 56-TSSOP |
| 標準包裝： | 34 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 49 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 包裝： | 管件 |
| 其它名稱： | *COP8CCR9KMT8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
1/tC < 10 Hz—Ensured clock rejection.
Table 5-28. WATCHDOG Service Actions
Key
Window
Clock
Action
Data
Monitor
Match
Valid Service: Restart Service Window
Don't Care
Mismatch
Don't Care
Error: Generate WATCHDOG Output
Mismatch
Don't Care
Error: Generate WATCHDOG Output
Don't Care
Mismatch
Error: Generate WATCHDOG Output
5.16.3 WATCHDOG AND CLOCK MONITOR SUMMARY
The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted:
Both the WATCHDOG and CLOCK MONITOR detector circuits are inhibited during RESET.
Following RESET, the WATCHDOG and CLOCK MONITOR are both enabled, with the WATCHDOG
having the maximum service window selected.
The WATCHDOG service window and CLOCK MONITOR enable/disable option can only be changed
once, during the initial WATCHDOG service following RESET.
The initial WATCHDOG service must match the key data value in the WATCHDOG Service register
WDSVR in order to avoid a WATCHDOG error.
Subsequent WATCHDOG services must match all three data fields in WDSVR in order to avoid
WATCHDOG errors.
The correct key data value cannot be read from the WATCHDOG Service register WDSVR. Any
attempt to read this key data value of 01100 from WDSVR will read as key data value of all 0's.
The WATCHDOG detector circuit is inhibited during both the HALT and IDLE modes.
The CLOCK MONITOR detector circuit is active during both the HALT and IDLE modes. Consequently,
the device inadvertently entering the HALT mode will be detected as a CLOCK MONITOR error
(provided that the CLOCK MONITOR enable option has been selected by the program). Likewise, a
device with WATCHDOG enabled in the Option but with the WATCHDOG output not connected to
RESET, will draw excessive HALT current if placed in the HALT mode. The clock Monitor will pull the
WATCHDOG output low and sink current through the on-chip pull-up resistor.
The WATCHDOG service window will be set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced for at least 2048 Idle Timer clocks following
HALT, but must be serviced within the selected window to avoid a WATCHDOG error.
The IDLE timer T0 is not initialized with external RESET.
The user can sync in to the IDLE counter cycle with an IDLE counter (T0) interrupt or by monitoring the
T0PND flag. The T0PND flag is set whenever the selected bit of the IDLE counter toggles (every 4, 8,
16, 32 or 64k Idle Timer clocks). The user is responsible for resetting the T0PND flag.
A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the
WATCHDOG should not be serviced for at least 2048 Idle Timer clocks following IDLE, but must be
serviced within the selected window to avoid a WATCHDOG error.
Following RESET, the initial WATCHDOG service (where the service window and the CLOCK
MONITOR enable/disable must be selected) may be programmed anywhere within the maximum
service window (65,536 instruction cycles) initialized by RESET. Note that this initial WATCHDOG
service may be programmed within the initial 2048 instruction cycles without causing a WATCHDOG
error.
When using any of the ISP functions in Boot ROM, the ISP routines will service the WATCHDOG
within the selected upper window. Upon return to flash memory, the WATCHDOG is serviced, the
lower window is enabled, and the user can service the WATCHDOG anytime following exit from Boot
ROM, but must service it within the selected upper window to avoid a WATCHDOG error.
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
83
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| COP8CCR9LVA7 | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| COP8CCR9LVA7/63 | 制造商:Texas Instruments 功能描述: |
| COP8CCR9LVA7/63SN | 功能描述:閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| COP8CCR9LVA7/NOPB | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| COP8CCR9LVA763SN | 制造商:National Semiconductor 功能描述:MCU 8-bit COP8 CISC 32KB Flash 5V 68-Pin PLCC |
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