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參數(shù)資料
| 型號： | DK1241A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Advanced Microstepping Motion Control Chipset |
| 中文描述： | 高級微步運(yùn)動控制芯片組 |
| 文件頁數(shù)： | 13/60頁 |
| 文件大小： | 422K |
| 代理商： | DK1241A |
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Pin Descriptions
The following tables provide pin descriptions for the MC1241A-series chipsets.
IC
I/O Chip Pinouts
I/O
Pin Name
Pin #
Description/Functionality
QuadA1
QuadB1
QuadA2
QuadB2
28
42
26
30
Quadrature A, B channels for axis 1 - 2 (input). Each of these 2 pairs of quadrature (A, B)
signals provide the position feedback for an incremental encoder. When the encoder is
moving in the positive, or forward direction, the A signal leads the B signal by 90 degs.
NOTE: Many encoders require a pull-up resistor on each of these signals to establish a
proper high signal (check the encoder electrical specifications)
NOTE: For MC1241A all 4 pins are valid. For MC1141A pins for axes 1 only are valid. Invalid
axis pins can be left unconnected
NOTE: These signals are not required for normal operation, but may be used if desired to
confirmmotor position.
Index encoder signals for axis 1-2 (input). Each of these 2 signals indicate the index flag
state fromthe encoder. A valid index pulse is recognized by the chip set when the index flag
transitions low, followed by the corresponding A and B channels of the encoder transitioning
low. The index pulse is recognized at the later of the A or B transitions. If not used this signal
must be tied high.
I/O
~Index1
~Index2
24
9
NOTE: For MC1241A both pins are valid. For MC1141A pins for axes 1 only are valid.
Invalid axis pins can be left unconnected.
NOTE: These signals are not required for normal operation, but may be used if desired to
confirmmotor position.
Home signals for axis 1-2 (input). Each of these signals provide a general purpose input to
the hardware position capture mechanism A valid home signal is recognized by the chipset
when the home flag transitions low. These signals have a simlar function as the ~Index
signals, but are not gated by the A and B encoder channels. For valid axis pins, If not used,
this signal must be tied high. See below for valid pin definitions for the MC1241A and
MC1141A.
I/O
~Home1
~Home2
13
23
NOTE: For MC1241A both pins are valid. For MC1141A pins for axes 1 only are valid.
Invalid axis pins can be left unconnected.
NOTE: These signals are not required for normal operation, but may be used if desired to
confirmmotor position.
DAC Select (output). This signal is asserted high to select any of the available DAC output
channels. For details on DAC decoding see description of DAC16Addr0-1 signals.
I/O chip clock (input). This signal is connected directly to the ClkOut pin (CP chip) and
provides the clock signal for the I/O chip. The frequency of this signal is 1/4 the user-provided
ClkIn (CP chip) frequency.
Phase shifted clock (input). This signal must be connected to I/OClkOut (I/O chip), and inputs
a phase shifted clock signal.
Phase shifted clock (output). This signal must be connected to I/OClkIn (I/O chip), and
outputs a phase shifted clock signal.
I/O chip to CP chip communication address (input). These 4 signals are connected to the
corresponding I/OAddr0-3 pins (CP chip), and together provide addressing signals to
facilitate CP to I/O chip communication.
I/O
DACSlct
33
I/O
CPClk
46
I/O
I/OClkIn
52
I/O
I/OClkOut
45
I/O
CPAddr0
CPAddr1
CPAddr2
CPAddr3
68
27
29
12
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