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參數(shù)資料
| 型號： | DK1241A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Advanced Microstepping Motion Control Chipset |
| 中文描述： | 高級微步運動控制芯片組 |
| 文件頁數(shù)： | 56/60頁 |
| 文件大小： | 422K |
| 代理商： | DK1241A |
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56
16-Bit Serial DAC Interface
The following schematic shows an interface circuit between the
MC1241A and a dual 16-bit serial DAC
Comments on Schematic
The 16 data bits and the two address bits fromthe CP chip are latched
in the two 74HC821 latches when the CP writes to address F hex, in
the address bits A0-A3. Three 74HC373 latches could also be used. If
this is a write to the DAC, DACSlct will be asserted during this CPU
cycle. The assertion of DACSlct will be latched by the fed-back and-or
gate, and the next clock will set the DACWR latch. The second clock
will set the second shift flop which will clear the DACL latch. Since this
latch has been cleared the third clock will clear DACWR providing a two
clock DACWR level. The fourth clock will clear the second shift flop
returning the systemto its original state waiting for the next DACSlct.
When the DACWR flop is set the 16 bit shift register implemented by
the 2 74FCT299's are parallel loaded with the 16 bits of data for the
DAC. The 4 bit counter, 74FCT161, is also parallel loaded to 0, and the
counter is enabled by clearing the ENP flop, which is contained in half
of the 74HCT109. The counter will not start counting nor the shift
register start shifting until the clock after the DACWR flop clears since
the load overrides the count enable. When the DACWR flop is cleared
the shift register will start shifting and the counter will count the shifts.
After 15 shifts CNT15 fromthe counter will go high and the next clock
will set the DACLAT flop and clear ENP flop. This will stop the shift after
16 shifts and assert L1 through L4 depending on the address stored in
the latch. The 16th clock also was counted causing the counter to roll
over to 0 and CNT15 to go low. The next clock will therefore clear the
DACLAT flop causing the DAC latch signal L1 through L4 to termnate
and the 16 bits of data to be latched in the addressed DAC. The control
logic is now back in its original state waiting for the next write to the
DACs by the CP.
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