參數(shù)資料
型號(hào)： DK1241A
廠商： Electronic Theatre Controls, Inc.
英文描述： Advanced Microstepping Motion Control Chipset
中文描述： 高級(jí)微步運(yùn)動(dòng)控制芯片組
文件頁(yè)數(shù)： 4/60頁(yè)
文件大小： 422K
代理商： DK1241A
4
Electrical Characteristics
Overview
The MC1241A consists of two 68 pin PLCC's both fabricated in CMOS.
The Peripheral Input/Output IC (I/O chip) is responsible for interfacing
to the host processor and to the position input encoders. The Command
Processor IC (CP chip) is responsible for all host command, trajectory,
and mcrostep computations, as well as for outputting the PWMand
DAC signals.
The following figure shows a typical systemblock diagram along with
the pin connections between the I/O chip and the CP chip.
Encoder
(1-2 axis)
Host
Processor
CP
I/O
Data4-11
I/OAddr0-3
I/OWrite
I/OCntrl0-3
ClkOut
Amplifier
(1-2 axis)
Motor
(2 axis)
The CP and I/O chips function together as one integrated motion
processor. The major components connected to the chip set are the
optional encoder (2, or 1 axes), the motor amplifier (2, or 1 axes), and
the host processor.
The encoder signals are input to the I/O chip in quadrature format. Two
signals encode the position, and an optional index signal contains a
once-per-rotation locating signal.
The chipset's motor output signals are connected to the motor amplifier.
Two types of output are provided; PWM(pulse width modulation), and
DAC-compatible signals used with an external DAC (digital to analog
converter). In addition 2-phase as well as 3-phase stepping motors are
supported. Because the output signals are in mcrostepping format, two
phased signals are provided per axis, with the relative phasing of the
two signals depending on the motor type (2-phase or 3-phase).
The host processor is interfaced via an 8-bit bi-directional bus and
various control signals. Host communication is coordinated by a
ready/busy signal, which indicates when communication is allowed.
Interconnections between the two chips consist of a data bus and
various control and synchronization signals. The following table
summarizes the signals that must be interconnected for the chipset to
function properly. For each listed signal the I/O chip pin on the left side
of the table is directly connected to the pin to the right.
I/O Chip Signal
Name
CPData4
CPData5
CPData6
CPData7
CPData8
CPData9
CPData10
CPData11
CPAddr0
CPAddr1
CPAddr2
CPAddr3
CPCntr0
CPCntr1
CPCntr2
CPCntr3
CPWrite
CPClk
I/O Chip
Pin
18
5
6
7
8
17
3
1
68
27
29
12
20
36
22
63
2
46
CP Chip
Signal Name
Data4
Data5
Data6
Data7
Data8
Data8
Data10
Data11
I/OAddr0
I/OAddr1
I/OAddr2
I/OAddr3
I/OCntr0
I/OCntr1
I/OCntr2
I/OCntr3
I/OWrite
ClkOut
CP Chip
Pin
50
49
46
43
40
39
36
35
28
9
6
5
16
18
68
67
15
19
For a complete description of all pins see the 'Pin Descriptions'
section of this manual.
Absolute Maximum Ratings
Unless otherwise stated, all electrical specifications are for both
the I/O and CP chips.
Storage Temperature, Ts.....................-55 deg. C to +150 deg. C
Supply Voltage, Vcc.............................-0.3 V to +7.0 V
Power Dissipation, Pd..........................650 mW (I/O and CP
combined)
Operating Ratings
Operating Temperature, Ta.................0 deg. C to +70 deg. C*
Nomnal Clock Frequency, Fclk...........25.0 Mhz
Supply Voltage, Vcc.............................4.75 V to 5.25 V
*Industrial and Mlitary operating ranges also available. Contact your
PMD representative for more information
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