參數(shù)資料
型號(hào)： DK1241A
廠商： Electronic Theatre Controls, Inc.
英文描述： Advanced Microstepping Motion Control Chipset
中文描述： 高級(jí)微步運(yùn)動(dòng)控制芯片組
文件頁數(shù)： 28/60頁
文件大?。?/td> 422K
代理商： DK1241A
28
the chip set for various possible conditions. This chip set-initiated signal
is known as a host interrupt.
Several chip set conditions may occur that can result in the generation
of a host interrupt. Whether these conditions in fact interrupt the host is
controllable for each condition and for each axis. The mechanismused
to control each condition is a mask register.
The interrupt conditions correspond to bits 0-7 and 11 of the
status register (the axis event flags), described in the previous
section. These conditions are summarized below:
Motion Complete
Wrap-around condition
Break Point Reached
Occurs when the profile is complete
Occurs when the axis position wraps.
Occurs when a breakpoint condition has
been satisfied.
Occurs when the encoder index pulse or
home pulse has been captured
Occurs when the maximumposition
error set for a particular axis has been
exceeded
Occurs when the negative over-travel
limt switch is active
Occurs when the positive over travel
limt switch is active
Occurs when a host communication
sequence causes a command error
condition
Position Capture
Received
Motion Error
Negative Limt Switch
Positive Limt Switch
Command Error
When one of these interrupt conditions occur for a particular axis, the
host interrupt line is made active. At this point the host can respond to
the interrupt (although the current I/O operation should be completed),
but it is not required to do so
When the host has completed processing the interrupt, it sends a
command that clears the interrupt conditions for a particular axis, the
RST_INTRPT command.
This command includes a "clearing mask" as an argument, which
allows one interrupt to be cleared at a time.
Bits cleared by the RST_INTRPT command are the exact same bits
as those cleared by non-interrupt commands such as
RST_STATUS and CLR_STATUS. In each case the bits affected are
the status word bits 0-7.
Interrupts occur for a particular axis. If the user is currently
programmng parameters on axis #1 and an interrupt occurs on axis #2,
it is the host's responsibility to change axis number to 2 if this is the
appropriate response to an interrupt on that axis. If more than one axis
interrupt condition becomes active at exactly the same time, then the
axis with the lowest number will generate the interrupt first.
The following host commands are used in managing interrupts:
(See Host Command reference for complete information)
SET_INTRPT_MASK
Sets the interrupt conditions mask
GET_INTRPT
Returns the status of the interrupting axis
(including the interrupting axis #). The
current axis #is not altered by this
command
Changes the current axis #to the
interrupting axis. This is a 'time saver'
command which performs the dual
operations of getting the interrupting axis
#and switching to that axis in one
command.
Clears particular conditions for the
interrupting axis. The current axis #is not
altered by this command.
SET_I
RST_INTRPT
To facilitate determning the nature of the interrupt, the status register
holds the axis # allowing the interrupting axis #to be determned.
The following represents a typical sequence of interrupt conditions and
host responses. Assume for the purposes of this example that an axis
(not the current axis) has hit a "hard stop" causing an essentially
instantaneous motion error, as well as a positive limt switch trip. Also
assume that the interrupt mask for this axis was set so that either
motion errors or limt switch trips will cause an interrupt
Event
Host action
motion Error & limt switch trip
generates interrupt
interrupting axis status
returned by chipset, current
axis set to interrupting axis.
host sends SET_I command
host detects motion error & limt
switch flags are set, recovers from
motion error first.
host sends: RST_INTRPT 00EF,
clearing motion error bit
-
chipset clears motion error bit
and disables host interrupt line
Because limt switch interrupt
is still active chipset
immediately generates
interrupt for limt switch
interrupting axis status
returned by chipset, current
axis set to interrupting axis.
host sends SET_I command
host detects that neg. limt switch
trip flag is set, performs recovery
for limt switch trip.
host sends RST_INTRPT 00DF,
clearing pos. limt switch bit
-
chipset clears limt switch bit
and disables host interrupt line
At the end of this sequence, all status bits are clear, the interrupt line is
inactive, and no interrupts are pending.
Note that it is not required to process multiple interrupts separately (as
is shown in the example). It is perfectly valid to process 2 or more
interrupt conditions at the same time, and to then send a RST_INTRPT
command with a mask that clears multiple bits at the same time.
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