參數(shù)資料
型號(hào)： DLKPC192S
英文描述： 10Gbps Ethernet LAN Physical Coding Sublayer (PCS) Device
中文描述： 10Gbps的以太網(wǎng)物理編碼子層（PCS）設(shè)備
文件頁(yè)數(shù)： 12/25頁(yè)
文件大?。?/td> 360K
代理商： DLKPC192S
!
SLLS536
–
AUGUST 2002
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MDIO management interface (continued)
Following the turnaround bits are 16 data bits. These are the values to be written to the addressed register during
write commands, or they are the values read from the addressed register during read commands.
During the bit time after the last data bit, the data signal may be released and the pullup on the line will bring
the data signal back to its idle state of all 1s.
Bit ordering is summarized in Table 1.
Table 1. MDIO Command Description
PRE
ST
OP
PHY AD
REG AD
TA
DATA
IDLE
READ
1...1
01
10
AAAAA
RRRRR
Z0
DDDDDDDDDDDDDDDD
Z
WRITE
1...1
01
01
AAAAA
RRRRR
10
DDDDDDDDDDDDDDDD
Z
A4
A0
R4
R0
0
1
0
1
MDC
MDIO
D15
D0
0
32 1s
HiZ
Preamble
SFD
Read
Code
PHY
Address
Register
Address
Data
Idle
Turn
Around
Figure 10. Management Interface Read Timing
A4
A0
R4
R0
D15
D0
0
1
1
0
1
0
MDC
MDIO
Preamble
SFD
Read
Code
PHY
Address
Register
Address
Data
Idle
Turn
Around
32 1s
Figure 11. Management Interface Write Timing
The MDIO management interface allows up to 32 16-bit internal registers. Sixteen registers are reserved by the
IEEE 802.3-2000 standard for definition and 16 are assigned for vendor-specific usage. The DLKPC192S
implements five registers defined by the proposed IEEE 802.3ae standard and four vendor-specific registers.
The IEEE-defined registers are listed in Table 2. The bit usage within these registers is defined in Table 3,
Table 4, Table 5, and Table 6. The vendor-specific registers are defined in Table 7. The bit usage within these
registers is defined in Table 8, Table 9, Table 10, and Table 11.
Table 2. MDIO Registers
REGISTER ADDRESS
REGISTER NAME
DEFINITION
0
Control
See Table 3
1
Status
See Table 4
2,3
PHY identifier
See Table 5
4
–
14
Not applicable
15
Extended status
See Table 6
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