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參數(shù)資料
| 型號(hào)： | DLKPC192S |
| 英文描述： | 10Gbps Ethernet LAN Physical Coding Sublayer (PCS) Device |
| 中文描述： | 10Gbps的以太網(wǎng)物理編碼子層（PCS）設(shè)備 |
| 文件頁(yè)數(shù)： | 22/25頁(yè) |
| 文件大?。?/td> | 360K |
| 代理商： | DLKPC192S |
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SLLS536
–
AUGUST 2002
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
XSBI (continued)
The XSBI receive interface timings are detailed in Table 13, and shown in Figure 13. Note, the phase
relationship is such that the positive side of the differential clock needs to rise
in the middle of the data
. This
is in contrast to the transmit XSBI interface. On that interface, the positive side to the clock is in phase with the
data. To successfully loop the transmit path to the receive path of this PCS device you must attach TXCP to
RXCN and TXCN to RXCP.
50%
50%
RXC
RXD(15:0)
t(HOLD)
t(SETUP)
t(PERIOD)
Valid Data
Valid Data
Figure 13. XSBI Receive Timing Diagram
Table 13. XSBI Receive Timing
PARAMETER
MIN
TYP
MAX
UNIT
t(PERIOD)
t(DUTY)
t(SETUP)
t(HOLD)
PMA_RX_CLK period
1.551515
ns
PMA_RX_CLK duty cycle
45%
55%
Data-setup before RXC
300
ps
Data-hold after RXC
300
ps
XGMII
50%
50%
TC
TD(31:0)
KG(3:0)
t(SETUP)
t(HOLD)
t(SETUP)
t(HOLD)
t(PERIOD)
Valid Data
Valid Data
Valid Data
Figure 14. XGMII Transmit Timing Diagram
Table 14. XGMII Transmit AC Specification
PARAMETER
MIN
TYP
MAX
UNIT
t(PERIOD)
t(SETUP)
t(HOLD)
t(DUTY)
TC transmit clock (received by DLKPC192S)
6.4
ns
Data-setup to rising or falling edge of TC
480
ps
Data-hold from rising or falling edge of TC
480
ps
TC duty cycle
40%
60%
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| DLKPC192SGNT | 功能描述:IC ETHERNET LAN PCS 289-PBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話(huà) 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤(pán)（4x4） 包裝:帶卷 (TR) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱(chēng):296-25223-2 |
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