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參數(shù)資料
| 型號(hào)： | DLKPC192S |
| 英文描述： | 10Gbps Ethernet LAN Physical Coding Sublayer (PCS) Device |
| 中文描述： | 10Gbps的以太網(wǎng)物理編碼子層（PCS）設(shè)備 |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 360K |
| 代理商： | DLKPC192S |
!
SLLS536
–
AUGUST 2002
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
transmission (continued)
transmit gearbox
The function of the transmit gearbox is to convert the 66-bit encoded data stream coming out of the 64b/66b
encoder into a 16-bit-wide data stream to be sent out on the XSBI bus to the physical media attachment (PMA)
device. While the effective bit rate of the 66 bit data stream is equal to the effective bit rate of the 16-bit XSBI
bus, the clock rates of the two buses are of different frequencies, thus the need for the gearbox.
XSBI transmit data bus
The connection to the PMA is via a 16-bit wide LVDS parallel data bus. Data is placed on the TXP[0:15]/
TXN[0:15] terminals. The LVDS clock on TXCP/TXCN clocks the data. Data is valid on the falling edge of TXC.
The data and clock signals are aligned as shown in Figure 5. A differential reference clock input is used as the
clock source to generate the output timing. The reference input clock is provided on XBICP/XBICN terminals.
A 100-
on-chip termination resistor is placed differentially at the LVDS input pair for the reference clock.
Detailed timing information is provided later in the
XSBI
paragraph of the
timing
—
reference clock
section.
TXCP/
TXCN
TXP[0:15]
TXN[0:15]
Figure 5. XSBI Transmit Output Timing Waveform
transmission latency
The data transmission latency of the DLKPC192S is defined as the delay from the edge of the XGMII transmit
clock when valid data is latched on the XGMII to the rising edge of the XSBI transmit clock, TXP/TXN, when
the last bit of the same data is output on the XSBI interface. The latency (T
LATENCY
) is measured in TXC clock
periods. The maximum latency is 99 TXC clock periods. If the latency is not an exact multiple of TXC clock
periods, then the latency value is rounded down to the next lower number of TXC clock periods for the minimum
latency and rounded up to the next higher integer number of TXC clock periods for the maximum latency.
B
A
AB
B
BC
A
C
TC
TXD[0:31]
KG[0:3]
TXCP/
TXCN
TXDP[0:15]
TXDN[0:15]
T(Latency MAX)
T(Latency MIN)
Figure 6. Transmitter Latency
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| DLKPC192SGNT | 功能描述:IC ETHERNET LAN PCS 289-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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