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參數(shù)資料
| 型號： | DLKPC192S |
| 英文描述： | 10Gbps Ethernet LAN Physical Coding Sublayer (PCS) Device |
| 中文描述： | 10Gbps的以太網(wǎng)物理編碼子層（PCS）設(shè)備 |
| 文件頁數(shù)： | 16/25頁 |
| 文件大小： | 360K |
| 代理商： | DLKPC192S |
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SLLS536
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AUGUST 2002
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
clocks
There are five interfaces on the DLKPC192S device: the XGMII transmit interface, the XGMII receive interface,
the XSBI transmit interface, the XSBI receive interface, and the MDIO interface (see Figure 1).
The XGMII transmit and receive interfaces operate at the same frequency and are specified identically. While
the clocks associated with the XGMII interface share specifications, the DLKPC192S places no requirement
that these clocks operate at exactly the same rate or have any phase relationship to each other. TC is the
transmit clock and is an input to the DLKPC192S. RC is the receive clock and is an output of the DLKPC192S.
RC is generated from a reference clock, RFC, which is an input to the DLKPC192S. RFC is input using LVDS
on terminals RFCP/RFCN. The two clock input signals associated with the XGMII transmit and receive
interfaces, TC and RFC, are expected to run continuously.
The XSBI transmit and receive interfaces operate at the same frequency and are specified identically. While
the clocks associated with the XSBI interface share specifications, the DLKPC192S places no requirement that
these clocks operate at exactly the same rate or have any phase relationship to each other. RX is the receive
clock and is an input to the DLKPC192S. TX is the transmit clock and is an output of the DLKPC192S. TX is
generated from a reference clock, XBIC, which is an input to the DLKPC192S. XBIC is input using LVDS on
terminals XBICP/XBICN. The two clock input signals associated with the XSBI transmit and receive interfaces,
RX and XBIC, are expected to run continuously.
The MDIO interface uses a clock (MDC) to strobe data into or out of the DLKPC192S. While there are maximum
frequency requirements for this clock, there is no minimum frequency. A system implementation, providing it
meets all of the other requirements for the MDIO interface, need not provide a continuously running MDC clock
signal.
power-on reset
The DLKPC192S uses an external power-on reset. Upon application of minimum valid power, power-on reset
may be removed as required by the system. While the DLKPC192S is being held reset: the XGMII outputs,
including the RC clock output are held low; the XSBI outputs are forced to toggle. Reset may be applied at
anytime. It is recommended that when reset is asserted that reset be held for a minimum of 1 microsecond (after
minimum valid power is applied). All clock inputs are expected to be valid at the time that reset is deasserted.
Shortly after a reset has occurred, the DLKPC192S begins outputting local fault and idle characters on the
XGMII interface and properly encoded local fault and idle characters on the XSBI interface. The local fault
characters are generated at the output of the FIFOs. For the transmit path, the local fault character must
propagate through the DLKPC192S before it can appear on the XSBI output.
For the transmit path, local faults continue to be generated until:
1.
At least eight valid idle or replacement character sets are transmitted to the DLKPC192S across the XGMII
interface, at which time the XGMII data is routed to the transmit FIFO.
2.
The transmit FIFO is filled to its midpoint (approximately 32 bytes or 8 XGMII transfers), at which time
transferring of data out of the FIFO is enabled.
3.
The data from the FIFO propagates through the 64b/66b encoder and the transmit gearbox and appears
on the XSBI transmit bus.
For the receive path, local faults continue to be generated until:
1.
Frame lock can be established using the input at the XSBI receive interface.
2.
The data propagates through the 66b/64b decoder, through the receive FIFO and appears on the XGMII
receive bus.
The MDIO interface accepts valid commands immediately following the deassertion of the reset signal.
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