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參數(shù)資料
| 型號： | DLKPC192S |
| 英文描述： | 10Gbps Ethernet LAN Physical Coding Sublayer (PCS) Device |
| 中文描述： | 10Gbps的以太網(wǎng)物理編碼子層（PCS）設(shè)備 |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 360K |
| 代理商： | DLKPC192S |
!
SLLS536
–
AUGUST 2002
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Table 3. Control Register Bit Definitions (Register 0)
BIT(S)
NAME
DESCRIPTION
READ/WRITE
0.15
Reset
Logically ORed with the inverse of RSTN terminal
1 = Global resets including FIFO clear
0 = Normal operation
When the reset bit is set to one, it automatically clears itself to zero upon completion of the reset
function.
Read/write
Self-clearing
0.14
Loopback
1 = Enable loopback mode
0 = Disable loopback mode (default)
When enabled, the transmit XSBI bus signals are internally routed to the receive XSBI bus
signals. The transmit XSBI output terminals are held at zero and the receive XSBI input terminals
are ignored when loopback is enabled. This mode requires the TXCP/N output clock to be
connected to the RXCP/N input clock. The first few transitions of the RXCP/N clock are required
for the device to come out of reset.
Read/write
0.13
Power Down
1 = Power-down mode is enabled.
0 = Normal operation (default)
When enabled, all sections of the DLKPC192S, with the exception of the MDIO interface logic,
are held reset and the internal clock distribution is disabled to minimize power usage. All inputs
to the DLKPC192, except for those related to the MDIO interface, are ignored. All outputs remain
driven, but are held at steady states. A reset is required after the part is subsequently powered
back up.
Read/write
0.12:0
Reserved
Write as 0. Ignore on read
—
Table 4. Status Register Bit Definitions (Register 1)
BIT(S)
NAME
DESCRIPTION
READ/WRITE
1.15:11
Read returns 10000b.
Read-only
1.10
PCS link status
1 = Link up when both the transmit path and receive path are functional
0 = Link down
Read-only
1.9
PCS high BER
1 = High BER. When 64b/66b receiver is detecting a BER > 10E
–
4.
0 = Low BER. When 64b/66b receiver is detecting a BER < 10E
–
4.
Note, return of low indication requires 250
μ
s following high BER detection.
1 = PCS synchronized to received frames
0 = PCS not synchronized to received frames
Read-only
1.8
PCS sync done
Read-only
1.7:0
Reserved
Read returns 0
Read-only
Table 5. PHY Identifier Bit Defintions (Registers 2, 3)
BIT(S)
NAME
DESCRIPTION
READ/WRITE
2.15:0
Bits 3:18 of the organizationally unique identifier (OUI) for Texas
Instruments
Read returns 0x8000.
Read-only
3.15:10
Bits 19:24 of the OUI for Texas Instruments
Read returns 0x14.
Read-only
3.9:4
Model number
Read returns 0x04.
Read-only
3.3:0
Revision number
Read returns 0x0 (subject to change).
Read-only
(3.15:0)
Complete register value (informational)
Read returns 0x5040 (subject to change).
Read-only
Table 6. Extended Status Register Bit Defintions (Register 15)
BIT(S)
NAME
DESCRIPTION
READ/WRITE
15.15:12
Various configurations
Read returns 0
Read-only
15.11:0
Reserved
Read returns 0
Read-only
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| DLKPC192SGNT | 功能描述:IC ETHERNET LAN PCS 289-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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