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參數(shù)資料
| 型號： | DLKPC192S |
| 英文描述： | 10Gbps Ethernet LAN Physical Coding Sublayer (PCS) Device |
| 中文描述： | 10Gbps的以太網(wǎng)物理編碼子層（PCS）設備 |
| 文件頁數(shù)： | 7/25頁 |
| 文件大?。?/td> | 360K |
| 代理商： | DLKPC192S |
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SLLS536
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AUGUST 2002
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description
transmission
The DLKPC192S accepts data with appropriate control coding on the 10-Gbps media-independent interface
(XGMII) as defined in the proposed IEEE P802.3ae standard. Data to be transmitted is clocked from the XGMII
interface into a register bank. The data is then transferred into the transmission FIFO. Data is pulled from the
FIFO, encoded via the 64b/66b encoder, and then disassembled into 16-bit words by the transmission gearbox
and transferred out over the XSBI interface.
XGMII transmit data bus timing
From the XGMII, the DLKPC192S latches the data on transmit data bus TD[0:31] along with the associated byte
level control terminals, KG[0:3]. Data is latched on both the rising and falling edges of the transmit data clock,
TC, as the XGMII interface is defined as a double-data-rate (DDR) interface. The basic timing is shown in
Figure 4. Detailed timing information is provided in the
XGMII
paragraph of the
timing—reference clock
section.
TC
TD[0:31]
KG[0:3]
t(SETUP)
t(HOLD)
t(SETUP)
t(HOLD)
Figure 4. XGMII Transmit Timing
transmit FIFO
The transmit FIFO provides sufficient buffer to compensate for both short-term clock-phase jitter and long-term
frequency differences between the input data rate at the XGMII interface to the output data rate at the XSBI
interface. Logic within the transmit FIFO provides the ability for the insertion or deletion of characters when the
transfer rate between the interfaces differs. If not for this ability, FIFO overruns or underruns could occur and
cause corruption of data. The logic within the transmit FIFO performs inserts or deletes, when necessary, in
such a way as to prevent corruption of Ethernet packets being transferred through the DLKPC192S.
64b/66b encode
To facilitate the transmission of data received from the media access control (MAC) layer, the DLKPC192S
encodes data received from the MAC using the 64b/66b encoding algorithm defined in the proposed IEEE
802.3ae standard. The DLKPC192S takes two consecutive transfers from the XGMII interface and encodes
them into a 66-bit code word. The information from the two XGMII transfers includes 64 bits of data and 8 bits
of control information. Not all combinations of control and data information are valid and, if the 64b/66b encoder
detects an invalid combination, the 64b/66b encoder replaces erroneous information with appropriately
encoded error information. The resulting 66-bit code word is then sent on to the transmit gearbox.
The encoding process is fully described within the proposed IEEE 802.3ae standard. It includes two steps, an
encoding step which converts the 72 bits of data received from the transmit FIFO block into a 66-bit code word
and then a scrambling step which scrambles 64 bits of encoded data using the scrambling algorithm x
57
+x
39
+1.
The 66 bits created by the encoder consists of 64 bits of data and a 2-bit synchronization field consisting of either
01 or 10. Only the 64 bits of data are scrambled, leaving the two synchronization bits unmodified. The two
synchronization bits allow the receive gearbox to obtain frame alignment and, in addition, ensure an edge
transition at least once in 66 bits of data. The encoding process allows a limited amount of control information
to be sent in-line with the data.
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