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參數(shù)資料
| 型號： | DLKPC192S |
| 英文描述： | 10Gbps Ethernet LAN Physical Coding Sublayer (PCS) Device |
| 中文描述： | 10Gbps的以太網(wǎng)物理編碼子層（PCS）設(shè)備 |
| 文件頁數(shù)： | 17/25頁 |
| 文件大?。?/td> | 360K |
| 代理商： | DLKPC192S |
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SLLS536
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AUGUST 2002
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
error handling
There are three types of errors that can be detected within the DLKPC192S. The three types are loss of frame
synchronization, bit errors, and FIFO errors (overruns or underruns). Loss of frame synchronization can only
occur on the receive path. Some, but not all, bit errors can be detected during the 64b/66b encode or decode
process. FIFO errors can occur only if a clock on either the XGMII or XSBI is significantly out of specification
or if there are insufficient and/or improper IPGs. If the clocks are within specification and a valid packet stream
is being sent or received, FIFO errors do not occur. Reaction to each type of error is described in the following
paragraphs.
The DLKPC192S resets frame synchronization at power-up or reset. Until frame synchronization is
accomplished, the DLKPC192S outputs a local fault character on the receive XGMII bus. The link status is set
to zero (link down) whenever the local fault character is being generated. Once frame synchronization is
completed, the DLKPC192S can perform normal operations.
Bit errors typically occur on the receive path of the DLKPC192S but could also occur on the transmit path. Bit
errors can be detected on the receive side either by detection of a framing error or by detection of an error during
the 66b/64b decode process. Bit errors on the transmit path can only be detected during the 64b/66b encoding
process. While the DLKPC192S device may detect some bit errors, many of the errors will likely go undetected
as the functional definition of a PCS type device does not include a method for reliable detection. If a bit error
is detected, the response by the DLKPC192S is to replace the received data containing the error with an
encoded control value signifying that an error occurred. Basically, the corrupted data is replaced with defined
error characters. If the rate of bit errors is high enough, frame synchronization could be lost. If frame
synchronization is lost, the DLKPC192S begins generating local fault characters. Because frame
synchronization is a function of the receive path and not the transmit path, local fault character generation as
a result of bit errors can occur only on the receive path.
The FIFOs within the DLKPC192S are sufficient to handle differences in clock rates between the XGMII and
the XSBI interfaces. Differences in clock rates are likely to occur, but only within specified limits. The depth of
the DLKPC192S FIFOs, the maximum packet sizes and the minimum interpacket gaps (IPGs) specified by the
Ethernet standards, along with the algorithms implemented within the DLKPC192S ensure that the FIFOs never
underrun or overrun during normal operation. If there is a system malfunction that causes the inputs to the
DLKPC192S to go out of specification, it is possible that the DLKPC192S could experience a FIFO underrun
or overrun. If the DLKPC192S detects such a condition, it sets an error condition flag in the vendor specific
registers, resets the link status, and generates local fault on the receive XGMII bus. The DLKPC192S must be
reset (soft or hard) to clear this error condition.
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